Feedback on this page
Company
Products
Technologies
Events
Support
Downloads
Partners
Design Creation
Schematic / Block Diagram Editor
HDL Text Editor
State Machine Editor
FPGA Project Management
IP Core Generator
Code to Graphics
Testbench Generation
Documentation (HTML/PDF)
Verification
VHDL Simulation
Verilog Simulation
SystemC
SystemVerilog
Assertions (PSL, SVA and OVA)
Acceleration/Emulation
Prototyping
Code Coverage
Design Rule Checker (LINT)
Specialty Solutions
In-Hardware Simulation
DO-254 Compliance
MATLAB/Simulink Co-Simulation
Verification IP
HDL Regression Manager
NIOS II Co-Verification
ARM Co-Verification
Actel RTAX Prototyping
Messages
News and Events
Upcoming Event
Active-HDL 7.3 Productivity Training Seminar
Using HDL Simulation for Xilinx Virtex-5 FPGAs
From Press Room
Aldec Delivers Clock Domain Crossing (CDC) Solution
Aldec Enhances Entire EDA Suite with Key Verification Methodologies
Aldec Releases Riviera-PRO™ 2008.06 HDL Simulator. Including New Assertions Waveform Viewer and Seamless debugging of SystemC/C++ and HDL