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Aldec, Inc., today announces the latest release of its mixed-language, FPGA Design & Simulation Platform, Active-HDL™ Student Edition for Mixed-Language Design Entry and Simulation contains many new and exciting features and is available as a free download for university students.

 

Active-HDL Student Edition includes a “load and go” license. Students may begin using immediately after install. License is valid until December 31, 2017.

 

Download Active-HDL™ Student Edition

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Active-HDL Student Edition

Design Creation

  • New Net Properties dialog box that allows specifying the properties of a wire, bus, composite type, global connector, terminal, or compound bus
  • Enhanced Design Rule Check(DRC) message in Block Diagram Editor
  • New Labeling options dialog box that defines how to assign the labels for the specified nets
  • Numerous new options added to settings of Block Diagram Editor and HDL Editor to improve the productivity of designers
  • Performance improvements for handling multipage Block Diagram Editor files

Simulation & Debugging

  • Introducing contributing signals - called contributors in waveform viewer that are specified as the input signals to the process driving the given signal
  • Enhancements made to VHDL-2008 and SystemVerilog (Design Constructs)

Design Flow Manager

  • Xilinx Vivado 2015.4
  • Altera™ Quartus Prime 15.1 Synthesis & Implementation
  • Lattice™ Diamond LSE 3.6
  • Microsemi® Libero SoC 11.6

Installation

  • Default installation path for Active-HDL Student Edition has been changed to: C:\Aldec\ Active-HDL Student Edition
  • Official support for Windows 10 has been added
  • 3D mouse devices are now supported by the Block Diagram Editor, the Symbol Editor, and the State Diagram Editor
 
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About Active-HDL™

Active-HDL™ is an FGPA veteran tool that has been helping FPGA designers for more than 15 years. It is an HDL-based FPGA Design and Simulation solution that supports the newest FPGA devices available from all leading FPGA vendors. The high-performance, mixed-language simulation solution interfaces with nearly one hundred twenty (120) third party vendor tools and provides FPGA designers a single platform that can be used independently of the targeted FPGA design flow. Active-HDL 10.3 supports design creation and simulation of the newest industry-leading FPGA devices from Altera®, Lattice®, Microsemi™ (Actel), and Xilinx®.

Fast Track to Active-HDL: Part One - Recorded Webinar

Active-HDL Release Notes - New Features and Enhancements

View all Active-HDL Resources

  
       
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Aldec is committed to advancing education for both working and future engineers in leading-edge methodologies and tools by providing access to world-class tools, resources and training through its University Program. Aldec supports students with:

  • Resources and Training
  • Free Active-HDL Student Edition
  • EDU Pricing and Availability

For more visit www.aldec.com/products/university_programs.

  
     
 

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sales@aldec.com
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Printed version of site: www.aldec.com/en/aldec_update_active_hdl_student_033016