How to Design the New Generation of Reprogrammable Router/Switch Using Zynq FPGA

A high-performance router is an absolute must if you want to run a high-traffic network in which different devices need to transfer and receive data as fast as possible. A router with a powerful processor and sufficient local memory reduces data hiccups and minimizes message loading and buffering times. But is that enough?

Because of the huge amount of data that people now generate - combined with the wealth of communication protocols, such as Wi-Fi, Ethernet, USB, SFP, QSFP - high-performance, hardware re-programmable routers are becoming popular. That hardware re-programmability is being delivered through FPGAs, and utilizing one as the main ‘processor’ on the router makes it easy to add or modify desired modules such as encryption and compression.

Since the importance of decision-making and hardware acceleration is relatively high in routers, the Xilinx® Zynq™ FPGA is a good option, because it has an ARM processor core and an FPGA integrated into a single chip which can boost the decision-making and hardware acceleration processes. In this regard, Aldec offers a networking solution based on the Xilinx® Zynq™ FPGA. In this solution, a router/switch is designed using TySOM-2A-7Z030 embedded development board and an FMC-NET daughter card (figures 1 and 2, respectively).

Figure 1: TySOM-2A-7Z030	Figure 2: FMC-NET

Together the board and daughter card have six Ethernet connectors, two Wi-Fi/Bluetooth channels, one QSFP+ connector and four SATA connectors. The Ethernet connectors can be used for connecting laptops and PCs to the network. The USB ports can be used to connect external devices such as Hard Drives and printers to the network.

The QSFP+ connectors can be used for high speed data transactions such as transferring data between the server and the network. The SATA connectors can be used for adding traditional hard drives and/or SSDs to the network. Figure 3, shows the setup for the described router. 

Figure 3: Router configuration

To dig more into this design, let’s divide the Xilinx® Zynq™ structure to PS and PL. In the PS side, the ARM processor runs the OpenWrt Linux distribution which controls all the devices. OpenWrt is chosen because it provides a fully writable file system with package management; instead of trying to create a single, static firmware. This frees you from the application selection and configuration provided by the vendor and allows you to customize the device through the use of packages to suit any application. For more information about OpenWrt, visit OpenWrt webpage.

In the PL side, the Ethernet MAC modules and AXI 1G/2.5G are used. Also, 10Gb Ethernet subsystem cores for QSFP+ are implemented. The FMC-NET daughter card is connected to the PL side which expands the peripherals. Figure 4 shows the PL/PS connectivity inside the Zynq device.

Figure 4: PS and PL connectivity inside the Zynq device 

After inserting the uSD card, which provides the required data for the PL and PS sides, to the TySOM-2A-7Z030 embedded development board, the next steps are:

• Bootloader starts and programs the FPGA plus loads the system kernel
• OpenWrt kernel loads drivers and initializes devices and IP cores
• OpenWrt makes net interfaces and starts system services
• OpenWrt works and user can control system via dedicated website or text mode

As an example, imagine that the router is going to transmit network packages through the Ethernet interface. Here are the transmit and receive sequences/flows.

OpenWrt → CPU → AXI → MAC → RGMII → PHY → Ethernet Port → Transmitted network packet
OpenWrt ← CPU ← AXI ← MAC ← RGMII ← PHY ← Ethernet Port ← Received network packet

I did a quick review of Aldec’s networking solution in this blog, and it is worth mentioning that in addition to the Xilinx® Zynq™ based embedded development boards and FMC daughter cards, Aldec provides fully-prepared reference designs for different embedded solution applications such as ADAS, IoT, and Networking. To find out more information about these solutions, visit here.