No Risk No Fun

At the end of February, I attended the Aero Show in India - and what a show it was. So many exhibitors from around the world, including all main players from the commercial and military sides of the aerospace industry.

Visitors could see everything required to build a modern aircraft; from small components like specialized ICs, cables and connectors up to big parts, such as the jet engines, landing gear assemblies and structural components.

But, for me, something was absent from the show? There was no real emphasis on safety. Does this mean we have already achieved everything we can terms of safety? That it’s taken as a given?

During the show, outside of the halls, visitors could see amazing aircraft demonstrations. Fighter aircrafts, helicopters and large transporter aircrafts, all demonstrating their nimbleness and the aerobatic skills of the pilots. It was all very impressive. But when I considered the demonstrations were directly above our heads in some cases I wondered if there was an element of “no risk no fun.”

The show ended happily, but during my 9-plus hour flight home my mind kept returning to the issue of “no risk, no fun” from an engineering perspective.

Incredibly, the “Design Assurance Guidance for Airborne Hardware” document RTCA DO-254 is fast approaching its 19^th birthday; as the ‘latest version’ is still technically that of April 19, 2000.

Let’s consider the recommendation to test FPGA design in the designated environment. For today's complexity of chips and the number of requirements the devices are able to implement, it is not possible to verify many of them by using board-level testing only.

How many combinations of inputs may not be achievable at all? Also, what a huge amount of work must be done by verification engineers to develop correct test procedures. This may result in the device not being well tested at all.

Luckily the guidance allows the use of an alternative method, and the industry has started to adopt techniques for chip-level testing in a standalone board.

Aldec provides a unique solution for this problem. Our CTS™ not only allows for exhaustive testing of the hardware, but it also spares engineers from making all the test procedures. You simply use your waveform from an RTL simulation as the source of input signals and as the golden vectors, launch the hardware (CTS) and then compare results against the simulation.

Back to the show. Many engineers visited our booth and were very interested in improving their verification processes for the certification of airborne electronic hardware. They realized that in using our CTS they could meet their obligations to minimize risk through comprehensive test coverage and, through the automation we provide, free up their time for some fun.