Robustness Testing for DO-254 Designs

Robustness testing is required for DO-254 DALs A and B. The purpose of robustness testing is to demonstrate that the device functions as intended - not only under normal operating conditions but also under abnormal operating conditions. Requirements-based tests usually cover test cases for normal conditions, but do not cover test cases for abnormal conditions. This is why applicants are expected to add robustness test cases to the verification plans to ensure the device functions as intended under all foreseeable conditions.

Examples of industry best-practice robustness tests include the following:
•    Invalid, interrupted and unexpected inputs
•    Invalid input timing (e.g., input that violates setup and hold time)
•    Out of range input address bus
•    Varying clock frequency and duty cycle within or outside clock tolerance
•    Varying input voltage

Robustness testing is difficult to achieve because of the lack of controllability on the FPGA inputs during board-level testing. Robustness testing is simplified with DO-254/CTS especially for test cases describing input and clock frequency variations. For the inputs, test cases for interrupted, invalid and unexpected inputs and out of range data bus can easily be implemented in the testbench, hence they can also be implemented and applied to the device during testing because DO-254/CTS utilizes the test vectors generated from simulation. For the clocks, DO-254/CTS provides complete controllability of the oscillators that are used for applying the test vectors, clocking the DUT and capturing the results. The clocks settings and variations are configurable and fully scriptable. The phase of clocks can be shifted with a step of 1/256 of clock's frequency while the input data remains constant. For example, if clock is running at 128MHz, the clock edge position can be shifted against the data with about 30ps step.

For more information regarding how DO-254/CTS can help with robustness testing, see related white paper DO-254: Increasing Verification Coverage by Test.