Best Design Practices For High-Capacity FPGA Devices Mariusz Grabowski, FPGA Design and Verification Engineer Like(0) Comments (0) With the latest FPGA technology advancements and release of high capacity devices such as Xilinx® Virtex®-7 and Altera® Stratix®-V, design teams face more challenges producing safe and clean HDL (RTL, FPGA) code. In this webinar, we focus on the design techniques that will result in the code running most optimally on the large FPGA designs, and be free of timing and synchronization issues.Recorded Webinar: Best Design Practices for High-Capacity FPGA Devices
