Are Metastability Monsters Lurking Beneath the Surface?

Every engineer and technician is aware of Murphy’s Law: “Anything that can go wrong will go wrong”.

The law appears when your elegantly-sculpted hardware and artfully-styled software code bang up against the real world of transition delays and timing requirements.

Over time, designers and trouble-shooters develop a healthy respect for Mr. Murphy and begin to anticipate when he is looking over their shoulder, learning “best practices” for recurring design problems.

The toughest design problems to trouble-shoot are ones that fail intermittently. A hidden flaw seems to pop up randomly with no certain pattern or definable cause.

Digital design and verification engineers have their own intermittent “monsters” to contend with. For these engineers, navigating through metastability pitfalls is one of their most formidable challenges.

Metastability monsters hatch at the fringe of clock domains, where clean, precisely-timed and synchronous signals leave their nice safe harbors to journey over an analog ocean of randomness and risk, where hidden traps can lure defenseless signals into captive lairs.

Not all signals will reach the safety of a familiar shore. Some will lag behind and beneath the rippling waves inside their digital eco-systems.

Metastability monsters may seem benign at first, but as more complexity is added to their habitat, more opportunity arises for wayward signals to fall within their restraining nets, and the desperate need for an experienced pilot becomes obvious.

To guide these signals and help them reach the friendly shore of a reliable clock domain, Aldec offers ALINT-PRO-CDC™, a new product within the company’s ALINT™ family of “linting” tools for Design Rules Checking (DRC).

ALINT-PRO-CDC is a Clock Domain Crossing (CDC) verification solution that provides engineers with best practices for analyzing clock domain crossing behavior early in the design cycle and offers analysis derived from both static and dynamic verification techniques, to ensure reliable cross-domains interactions.

Violations can be fixed and the design can then be iteratively re-compiled until the model conforms to the rule set’s best practices for naming convention, design structure, clock domain interaction, etc.

Rule sets used for linting can also be customized according to company policies, allowing consideration of which violations are more severe than others and which ones can be ignored safely.

For mission-critical safety applications, like DO-254 compliance requirements from the federal government, ALINT-PRO-CDC is a good complement to Aldec’s DO-254 solutions for the military and aerospace industries.

In January 2015, Aldec released ALINT-PRO-CDC for Clock Domain Crossing Verification. For more information, configurations or free evaluation download, visit https://www.aldec.com/products/alint-pro-cdc.

Highlights from ALINT-PRO-CDC 2015.01

• Can generate a SystemVerilog testbench for the design with structurally correct CDC paths. The testbench emulates the mestability effect in the design and includes appropriate assertions to verify valid use of synchronizers and their interactions with other logic.

• Assertions in the CDC testbench are generated for a synchronizer depending on its type. NDFF and MUX synchronizers assertions are provided.

• The generated testbench can be simulated in Aldec Riviera-PRO™ and Active-HDL™.

• Distinguishes registers by clock domains and detects cross-domain signal transfers within a design. The tool expects to see a proper synchronization circuit on the receiving clock domain side for each signal that crosses domain boundaries. If there is no synchronizer, or it is structurally incorrect, violations of corresponding rules are reported.

• The Schematic Viewer window presents a graphical view of a design netlist generated for the elaboration top-level units of a synthesized project, and provides convenient means for design navigation (expanding, zooming, cross-probing to source files). It shows elements (instances and primitives) that make up the top-level unit, as well as all the connections between them.

• ALINT-PRO-CDC includes a GUI mode with an intuitive interface that includes a Project Manager, HDL Editor, Library Viewer, Elaboration Viewer, Policy Editor, Violation Viewer, and Rule Description Viewer.

• Hardware Description Language support is provided for VHDL, Verilog and SystemVerilog.

• For more features, visit https://www.aldec.com/products/alint-pro-cdc.

ALINT-PRO-CDC is available in 32-bit and 64-bit versions that can run on Windows and Linux OS platforms support x86 and x86_64 CPU architectures. For a demonstration, please contact Aldec Sales at +1-702-990-4400 or sales@aldec.com.