Aldec Design and Verification Blog Trending Articles Navigating VUnit: A Practical Guide to Modifying Testing Approaches Speeding Up Simulation with VUnit for Parallel Testing Introduction to VUnit FPGA Design Verification in a Nutshell Versal ACAP Simulation Challenges Real-time SDR system with TySOM The Convergence of Emulation and Prototyping All Categories Corporate DO-254 Compliance Embedded Solutions Emulation/Acceleration FPGA Design Functional Verification High Performance Computing Requirements Management SoC and ASIC Prototyping SoC Design and Validation Specialized Applications Linting RISC-V designs with ALINT-PRO As the open-source RISC-V instruction set architecture (ISA) continues to gain momentum, the growing number of RISC-V design solutions, and their flexibility, creates a problem when choosing the most reliable and robust solution from a number of contenders.... Tags:ASIC,FPGA,HDL,Verification,Verilog,Design,Digital,IP,Linting,SoC,SystemVerilog Like(2) Comments (0) Read more Aldec Verification Tools Implement the ASIC Verification Flow Insights from Dr. Stanley Hyduke, Aldec Founder and CEO Aldec has, over the last 30 years, established itself as the preferred provider of high-performance, cost-effective verification tools for use in proving out complex FPGA designs. As the logic capacity and capability... Tags:Aceleration,ASIC,Emulation,Linting,Prototyping,Simulation,Verification Like(2) Comments (0) Read more A Comprehensive RTL Verification Solution for VHDL ALINT-PRO™ Design Rule Checking Solution On Thursday, November 19, I’ll be hosting a webinar to demonstrate Aldec’s RTL Verification Solution for VHDL, ALINT-PRO™ Design Rule Checking Solution. ALINT-PRO is Aldec’s design verification solution for RTL code... Tags:Coverage,Debugging,Linting,safety-critical,Verification,VHDL Like(2) Comments (0) Read more Are Metastability Monsters Lurking Beneath the Surface? Taming Clock Domain Crossing Issues with ALINT-PRO-CDC™ Every engineer and technician is aware of Murphy’s Law: “Anything that can go wrong will go wrong”. The law appears when your elegantly-sculpted hardware and artfully-styled software code bang up against the real world... Tags:Linting Like(2) Comments (0) Read more It’s Here! ALINT-PRO-CDC™ for CDC Verification Aldec’s new solution for complex multi-clock designs I am happy to announce, that today Aldec has released ALINT-PRO-CDC™ 2015.01. This solution enables verification of clock domain crossings and handling of metastability issues in complex, modern multi-clock designs.... Tags:ASIC,FPGA,Linting,safety-critical Like(2) Comments (0) Read more Averting CDC Roadblocks in FPGA Design Design Rule Checking Best Practices This being my first summer in Las Vegas, it is the first time I’ve experienced the rainy, desert monsoon season and the powerful flash floods it can bring. Last week one of those monsoons, powered by the remnants of Hurricane Norbert,... Tags:Design,FPGA,Linting,Simulation Like(2) Comments (0) Read more Averting Clock-Domain Crossing issues in FPGA Design A solution to your worst CDC nightmare A failing FPGA device in the field with a Clock Domain Crossing (CDC) issue is a true nightmare. The risk of CDC related failure is on the rise as FPGA-based SOC design complexity continues to mount... Tags:Coverage,Design,FPGA,Linting,SoC Like(2) Comments (0) Read more Much has changed in the last 30 years A New Year’s Reflection from Aldec’s founder and CEO When I first launched Aldec in 1984, home computers hadn’t quite taken off and innovations such as the compact disk and those oversized, power draining cellphones were still struggling to obtain mass acceptance.... Tags:Debugging,Design,Linting,Simulation,UVM,Verification Like(2) Comments (0) Read more
