Aldec Design and Verification Blog Trending Articles Navigating VUnit: A Practical Guide to Modifying Testing Approaches Speeding Up Simulation with VUnit for Parallel Testing Introduction to VUnit FPGA Design Verification in a Nutshell Versal ACAP Simulation Challenges Real-time SDR system with TySOM The Convergence of Emulation and Prototyping All Categories Corporate DO-254 Compliance Embedded Solutions Emulation/Acceleration FPGA Design Functional Verification High Performance Computing Requirements Management SoC and ASIC Prototyping SoC Design and Validation Specialized Applications Verification Effectiveness with Riviera-PRO: SystemVerilog Randomized Layered Testbench Understanding SystemVerilog Layered Testbench In this blog, I will discuss randomized layered testbenches used in SystemVerilog. We need to understand why we need it, ... Tags:Riviera-PRO,ASIC,Assertions,Co-simulation,Coverage,Debugging,Design,Documentation,FPGA,HDL,IEEE,OS-VVM,Randomization,Simulation,standards,SystemVerilog,UVM,Verification,Verilog Like(4) Comments (0) Read more Transitioning to Advanced Verification Techniques for FPGAs – Catch-22? A Guest Blog by TVS Founder and CEO, Dr. Mike Bartley Many FPGA designers find themselves in a catch-22: they recognise that their designs are becoming too complex for their current verification strategies BUT adopting advanced verification techniques (such as the Universal Verification Methodology – UVM) is... Tags:FPGA,Randomization,Verification,Coverage,Digital,IP,Simulation,Verilog,VHDL Like(2) Comments (0) Read more My First Example with OS-VVM CoveragePkg A Guest Blog from Alex Grove of FirstEDA Here in Europe, I recently had the opportunity to work with Jim Lewis, OS-VVM Chief Architect and IEEE 1076 Working Group Chair, on the first Advanced VHDL Testbenches & Verification training course.... Tags:Coverage,Design,FPGA,OS-VVM,Randomization,Verification,VHDL Like(3) Comments (1) Read more Why Randomize? Guest Blog with Jim Lewis, VHDL Training Expert at SynthWorks After presenting a conference paper on how to do OSVVM-style constrained random and intelligent coverage (randomization based on functional coverage holes), I received a great question, "Why Randomize?"... Tags:Coverage,OS-VVM,Randomization,VHDL Like(2) Comments (0) Read more
