Event Details

Time: 11:00 AM - 12:00 PM (PDT)

 

Abstract

This “Getting Started” presentation is for engineers who need to use the OSVVM AXI4 verification components (VCs) in their testbenches. Part 1 of this presentation provides a detailed walkthrough of creating a testbench environment that uses AXI4 VCs.

 

AXI4 VCs are probably the most complex VCs in the OSVVM library. This complexity is due to the AXI4 interface having five independent interfaces: Write Address, Write Data, Write Response, Read Address, and Read Data. Going further, the interface supports user configurable optional aspects of the interface – such as the ID and User fields.

 

In this presentation we examine the details of the test harness including the required context references, configuring the transaction interface, configuring the AXI interface, creating clock and reset, connecting the DUT to the OSVVM AXI interface record, and connecting to the AXI VCs.

 

We continue by examining how to size the AXI4 interface by sizing the unconstrained record elements of the AXI4 interface and OSVVM transaction interface records.

 

We wrap up by looking at how to use AXI4 VCs inside a DUT – such as with Zynq. In this situation, the DUT does not have a port for the transaction interface(s). To address this use model, OSVVM provides another set of AXI4 VCs that use OSVVM’s virtual transaction interface (VTI). These VCs all have Vti in their name, such as Axi4ManagerVti.vhd.

 

The Zynq subordinate interfaces (such as Axi4Memory) can share the same memory space. As a result, we look at how OSVVM configures multiple instances of the Axi4Memory to share their internal address space.

 

About OSVVM

OSVVM is a suite of libraries designed to streamline your VHDL entire verification process, boosting productivity and reducing development time. Each library provides independent capabilities, allowing selective adoption and a learn-as-you-go approach. Whether using directed or random testing, OSVVM facilitates writing concise and readable test cases for both unit/RTL tests and complex FPGA and ASIC tests.

 

OSVVM provides VHDL with verification capabilities that rival SystemVerilog + UVM. These include transaction-level modeling, verification components, co-simulation with software, randomized test generation, self-checking test support, verification data structures, comprehensive test reporting in HTML and text, and synchronization primitives.

 

With OSVVM and a good team lead, any VHDL engineer can do verification – and have fun doing it. As a result, having your entire team united in using OSVVM will simplify deploying VHDL engineers to projects.

 

SynthWorks has been using OSVVM for 25+ years in our training classes and consulting work. During that time, we have innovated new capabilities and evolved our existing ones to increase re-use and reduce effort and time spent.  

 

Why VHDL for verification? According to the 2022 Wilson Research Group Functional Verification Study, in the FPGA market, 66% use VHDL for design, 58% use VHDL for verification, and 28% use OSVVM.  Hence, VHDL is #1 for FPGA development and OSVVM is #1 for VHDL verification.

 

Webinar Duration:

• 50 min presentation/live demo
• 10 min Q&A

 

Presenter BIO

Jim Lewis,  VHDL Design and Verification Expert, Trainer, OSVVM developer, and IEEE VHDL Chair

Jim Lewis is an innovator and leader in the VHDL community. He has 30 plus years of design and teaching experience. He is the Chair of the IEEE 1076 VHDL Standards Working Group.  He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology.  He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice, he has created designs for print servers, IMA E1/T1 networking, fighter jets, video phones, and spacecraft. 

 

Whether teaching, developing OSVVM, consulting on VHDL design and verification projects, or working on the IEEE VHDL standard, Mr. Lewis brings a deep understanding of VHDL to architect solutions that solve difficult problems in simple ways.