Event Details

Time: 11:00 AM - 12:00 PM (PDT)

 

Abstract

This “Getting Started” presentation is for engineers who need to use the OSVVM AXI4 verification components (VCs) in their testbenches. Part 2 of this presentation focuses on how to write tests and configure the AXI4 VCs.

 

AXI4 VCs are probably the most complex VCs in the OSVVM library. This complexity is due to the AXI4 interface having 5 independent interfaces: Write Address, Write Data, Write Response, Read Address, and Read Data. Going further, the interface supports user configurable optional aspects of the interface – such as the ID and User fields.

 

In this presentation we examine the structure of OSVVM test cases, the AXI4 transaction API, how to do byte transfers, how to do burst transfers, how to handle arrays of VCs, how to configure AXI4 VC options, how to randomize delays for xValid or xReady, and how the test case can directly read or write values in the Axi4Memory.

 

As we look at the OSVVM transaction API we will note that it does not specify the byte enables. Instead, OSVVM determines the byte enables by looking at the width of the data and the lower bits of the address.

 

OSVVM’s burst interface is supported by FIFOs that are in the transaction interface. These FIFOs allow any size of std_logic_vector value to be pushed into them. This allows the burst interface to be used in either byte mode or word mode. In byte mode, the burst is a sequence of bytes that are assembled by the VC into interface words. This allows OSVVM to create test cases that are independent of the actual data bus width.

 

About OSVVM

OSVVM is a suite of libraries designed to streamline your VHDL entire verification process, boosting productivity and reducing development time. Each library provides independent capabilities, allowing selective adoption and a learn-as-you-go approach. Whether using directed or random testing, OSVVM facilitates writing concise and readable test cases for both unit/RTL tests and complex FPGA and ASIC tests.

 

OSVVM provides VHDL with verification capabilities that rival SystemVerilog + UVM. These include transaction-level modeling, verification components, co-simulation with software, randomized test generation, self-checking test support, verification data structures, comprehensive test reporting in HTML and text, and synchronization primitives.

 

With OSVVM and a good team lead, any VHDL engineer can do verification – and have fun doing it. As a result, having your entire team united in using OSVVM will simplify deploying VHDL engineers to projects.

 

SynthWorks has been using OSVVM for 25+ years in our training classes and consulting work. During that time, we have innovated new capabilities and evolved our existing ones to increase re-use and reduce effort and time spent.  

 

Why VHDL for verification? According to the 2022 Wilson Research Group Functional Verification Study, in the FPGA market, 66% use VHDL for design, 58% use VHDL for verification, and 28% use OSVVM.  Hence, VHDL is #1 for FPGA development and OSVVM is #1 for VHDL verification.

 

Webinar Duration:

• 50 min presentation/live demo
• 10 min Q&A

 

Presenter BIO

Jim Lewis,  VHDL Design and Verification Expert, Trainer, OSVVM developer, and IEEE VHDL Chair

Jim Lewis is an innovator and leader in the VHDL community. He has 30 plus years of design and teaching experience. He is the Chair of the IEEE 1076 VHDL Standards Working Group.  He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology.  He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice, he has created designs for print servers, IMA E1/T1 networking, fighter jets, video phones, and spacecraft. 

 

Whether teaching, developing OSVVM, consulting on VHDL design and verification projects, or working on the IEEE VHDL standard, Mr. Lewis brings a deep understanding of VHDL to architect solutions that solve difficult problems in simple ways.