Event Details View All Recorded Events Date Event Type Location Action Nov 20, 2024 VHDL/SystemVerilog RTL verification environment using cocotb ~ Test bench that can be written in Python VHDL/SystemVerilog RTL verification environment using cocotb ~ Test bench that can be written in Python Date: Wed, November 20, 2024 Time: 3:00 PM - 4:00 PM (JPT) Please note that this webinar will be conducted in Japanese! Webinar Tokyo, Japan Register
