Aldec delivers Rapid Debugging with UVM Toolbox™ to Interpret Complex UVM Verification Environments

Henderson, NV – August 5, 2014 – Aldec, Inc., announces the latest release of its mixed-language, advanced verification platform, Riviera-PRO™ 2014.06. This release extends Riviera-PRO’s already powerful visual mapping capabilities for UVM verification environments. Aldec introduces UVM Toolbox™ to interpret complex UVM verification environments into an easily readable, hierarchical format. With best-in-class SystemVerilog support and now more powerful UVM debugging environment, Riviera-PRO significantly increases the productivity of design and verification engineers.

"Riviera-PRO already allows visualizing the testbench architecture and data flow between UVM components with its signature UVM Graph tool” said Satyam Jani, Riviera-PRO Product Manager, “UVM Toolbox extends Riviera-Pro’s debugging capabilities with easy-to-read, tree-like hierarchy that allows users to quickly locate components within a UVM verification environment.”

UVM Toolbox displays object properties for components selected within the hierarchy and is synchronized with UVM Graph, Class Viewer and HDL Editor features within Riviera-PRO to deliver a seamless debugging experience.

The 2014.06 release of Riviera-PRO also includes numerous new features, enhancements, and performance optimizations. For additional information, tutorials, free evaluation download and What’s New Presentation, visit http://www.aldec.com/Products/Riviera-PRO.

About Aldec

Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com