Henderson, NV – February 2, 2016 – Aldec is a proud Gold Sponsor and presenter at Verification Futures 2016, a unique one day conference, exhibition and industry networking event organized by TVS. Scheduled to be held Thursday, February 4, 2016, in Reading, UK, Verification Futures is the largest dedicated ASIC and FPGA verification event in Europe.

 

Alex Grove, of Aldec Distributor, FirstEDA, is scheduled to present, ’Using FPGAs to accelerate verification of your next ASIC: Introducing the FPGA Co-emulator’. Alex is an expert on Aldec solutions with a particular focus on hardware-assisted verification and RTL simulation products. Below follows a brief abstract of his scheduled presentation.

 

Never has the need to accelerate verification been so great; reduced market windows, ever increasing complexity and a growing need for longer tests. Most ASIC IP and SoC platforms will be validated at some point using FPGAs; this task is typically known as ASIC FPGA prototyping. Such a prototype is the closest representation of the final silicon and typically used to validate and test software and perform at-speed testing of real world interfaces.

At the same time, FPGAs are increasingly being used for verification due to the performance and scalability of such systems. These systems are very different in their capabilities to that employed for ASIC FPGA prototyping. The use of FPGAs provides the greatest capability in terms of verification cycles and are ideal for regression. With the arrival of Xilinx’s UltraScale, the capability of FPGA-based verification has never been so great.

In this short presentation we will introduce the FPGA Co-emulator and discuss two typical use cases for such a system:

- The verification of hardware dependent software (HdS)

- UVM simulation acceleration

 

About Verification Futures

Verification Futures is organized by TVS to discuss the challenges faced in hardware verification. The event gives the opportunity for end users to define their current and future verification challenges and collaborate with the vendors to create solutions. It’s also an excellent opportunity to network and catch up with other verification engineers across Europe. Visit www.testandverification.com to register or to learn more.

 

About Aldec
Established in 1984, Aldec is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Emulation, Design Rule Checking, Clock Domain Crossing, VIP Transactors, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com

 

Henderson, NV – February 2, 2016 – Aldec, Inc., today announces the latest release of its requirements lifecycle management solution for FPGAs/SoCs, Spec-TRACER™ 2015.12. This release provides users the necessary features and capabilities for systematically managing Validation and Verification (V & V) data and artifacts of large and complex FPGA/SoC DO-254 projects.

 

“Organizations developing FPGAs/SoCs for DO-254 compliance have to produce an extensive amount of V & V data and artifacts,” said Louie De Luna, DO-254 Program Manager. “Data creation and management of this magnitude can get chaotic without a systematic approach and can result in significant project delays.”

 

The latest Spec-TRACER release delivers new advanced features, reference projects, designs, video tutorials (to enable users to easily implement and enforce requirements management), traceability, tests management, and project management for managing V & V data and artifacts.

 

To learn more, register for Aldec’s upcoming webinar, Efficient Management of DO-254 Validation and Verification.

 

Spec-TRACER 2015.12 New Features, Sample Projects and Video Tutorials

• The Parsers supports automatic capture of data and traceability based on regular expressions from .doc, docx, .vhd, .v, .sv, .psl and IBM® Rational® DOORS® objects.
• Import from DOORS and export to DOORS based on filter Views of DOORS formal modules. The functionality allows limiting number of objects imported from DOORS and exported to DOORS.
• The new Audio System sample project is the base for the new Traceability Tutorial using Parsers which presents how to build traceability from different sources by using Spec-TRACER parsers.
• New included video tutorials include how to build traceability, create projects and conduct impact analysis.

 

About Spec-TRACER™

Spec-TRACER is a unified requirements lifecycle management application designed to facilitate a requirements-based FPGA/SoC design and verification process. Spec-TRACER facilitates requirements capture, management, analysis, traceability, tests management and reporting. Spec-TRACER seamlessly integrates with windows-based simulation tools.

 

Availability

New customers and customers without current maintenance contracts are invited to contact their local Aldec Distributor to receive additional information on the latest release. For additional information about Spec-TRACER 2015.12 including tutorials, free evaluation downloads and What’s New Presentation, please visit www.aldec.com/Products/Spec-TRACER.

 

About Aldec

Established in 1984, Aldec is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Emulation, Design Rule Checking, Clock Domain Crossing, VIP Transactors, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com