Aldec @ DAC 2018: Presenting Innovative SoC Design & Verification Methodologies

Partitioning Design for Multi-FPGA Prototyping - Multi-FPGA partitioning has always been a challenge due to limited number of FPGA I/Os and FPGA-specific clocking tree. Aldec provides HES-DVM Prototyping toolbox that automates design partitioning for multiple FPGAs and allows connecting prototyped design with AMBA AXI bus to the workstation via ultra-fast HES Proto-AXI host interface. This year we will demonstrate the new features and improvements that include: Impact analysis tool for quick assessment of partitioning decisions, Automatic FPGA I/O assignment with serialization and System level critical path analyzer. The HES-DVM Prototyping mode shortens (from months to a week time) the first design setup for multi-FPGA platform and facilitates achieving a reliable prototype build running at tens of MHz rates that is sufficient for software development and testing with real world interfaces, devices and data streams.

Hardware-Software Co-debugging Using Hybrid QEMU/HES-DVM Co-emulation - QEMU is a generic and open source machine emulator that supports various computer hardware architectures including Intel x86 and ARM® Cortex® families. It can be connected with the Aldec HES-DVM™ emulation platform to provide a hybrid co-emulation environment for SoC designs. We will demonstrate the latest QEMU Bridge designed to provide connection between CPU subsystem in QEMU and custom hardware IP-Core run in the HES FPGA board and mapped as PCI Express device in QEMU. We will also show how software stack GDB debugger can be used in step-lock mode with the Aldec Hardware Debugger to provide full and deterministic view of the entire SoC.

In-Circuit Emulation (ICE) of Today's SoCs - ICE is a traditional approach to verification of emulated design with external peripherals for which real devices are connected to the emulator. Emulators based on FPGA prototyping boards have a significant advantage over dedicated emulation boxes which is larger number of different connectors. Moreover these connectors are tied up to different FPGAs on multi-FPGA boards facilitating external devices connection and design partitioning. With ICE it is often required that external device runs at its target speed which is higher than speed of emulated clocks. This is the case where speed adapter modules are used. They can be treated as a special kind of Verification IP that separates real clock domain from emulated clock and additionally buffers data transfers.

Aldec and Silvaco Mixed-Signal Simulation - Aldec and Silvaco® continue their efforts to provide robust mixed-signal solution based on high-performance tools such as Riviera-PRO Advanced Verification Platform and SmartSpice™ Parallel SPICE Circuit Simulator. The demo will show mixed-signal simulation and debug capabilities. We will show how the digital and analog domains can communicate and how user can obtain results of Verilog-AMS and Verilog-D co-simulation in Riviera-PRO user interface. Users can view the co-simulation results using Riviera-PRO Advanced Waveform Viewer and debug using Riviera-PRO debugging features.

SoC Simulation Environment for Mixed-Signal Designs - Today's SoC FPGA embedded designs present new verification challenges for both software and hardware engineers. Aldec provides a HW/SW co-simulation approach based on open-source QEMU that can be run together with Verilog-AMS from Silvaco SmartSpice. The demo will show how to prepare and simulate pulse-width modulation (PWM) module with analog output. The simulation flow combines Riviera-PRO Advanced Verification Platform, Open-Source QEMU and SmartSpice Parallel SPICE.

Simulation Environment for HLS Designs - High Level Synthesis (HLS) has gained lots of popularity over the last few years. As with any emerging technology there are also challenges associated with it. With HLS we face new verification challenges: How to test your C model? How to check it against multiple random scenarios? How does that correlate to your RTL Verification? We will be answering these questions and showing you how to do it in a friendly and easy to debug environment. We will be demonstrating how to verify C model generated from Vivado HLS using Riviera-PRO Advanced Verification Platform and SystemVerilog based UVM Connect library.

What’s New in VHDL 2018 and Open-Source Verification Methodology? - Aldec continues to actively support industry based initiatives related to hardware description languages. The newest is VHDL 2018 with OSVVM methodology. Riviera-PRO is one of the first early adopters of this new proposed IEEE 1076-2018 Standard. This demonstration will show you all aspects of modern verification base in VHDL. We will do an overview from methodology level to live working example. The demo will be done in cooperation with VHDL evangelist Jim Lewis.

Why do we need UVM Register Abstraction Layer? - While it is often necessary to access more specific details of UVM Register Layer classes, they are not accessible in their default state and can only reveal generic internal data. To gather data about registers, a specialized register layer is created via extensions that correspond to actual registers and memories, which is mapped to the design hierarchy. Designs can consist of a large number of registers each one with different register fields and specifications, where writing a model for these registers would be too time-consuming, so using a generator is necessary. The register generator available in Riviera-PRO takes register specifications and produces the equivalent register model in SystemVerilog code. Using an IP-XACT or CSV description a UVM environment can be generated. This demo will show how to go from preparing a UVM based environment to verifying your design in seconds.

Static Verification for FPGAs - In addition to all reset types support, ALINT-PRO adds various FPGA-specific CDC checks, such as enable-based synchronizer (instead of mux-based), ensuring that NDFF patterns do not synthesize in Shift Register Lookup table. ALINT-PRO also adds automated designs constraints generation feature, allowing FPGA designers to generate comprehensive design constraints at early stages of the FPGA implementation process. Finally, ALINT-PRO is capable to automatically import Xilinx® Vivado™ projects with the IP blocks. For each IP block, ALINT-PRO automatically extracts timing constraints, enabling smooth and easy process of Vivado projects verification in ALINT-PRO.

Finite State Machine Exploration and Checking - Finite State Machine (FSM) extraction enables designers to extract, visualize and verify designs with FSMs. The FSM Viewer Window presents all identified FSM structures in current design. Designers are able to visualize extracted FSM topology using convenient graphical interface. The FSM checking ruleset contains extensive number of various topological, naming and functional checks. It includes the identification of the redundant, deadlock and unreachable states and proper FSM resetting scheme. For the safety-critical designs, ALINT-PRO contains checks to ensure proper FSM reset behavior under heavy noise causing state corruption.

Reset and Reset Domain Crossing Analysis - Reset Structures exploration and verification allow designers to verify complex reset schemes and to ensure that the design always starts from a known deterministic state. Currently, ALINT-PRO is capable to extract and verify synchronous reset structures as well as non-resettable sequential elements. This feature allows ALINT-PRO to comprehensively verify reset logic in various types of FPGA designs. Additionally, along with Clock Domain Crossings (CDC), RDC is another source of metastability in designs with multiple resets. Same as CDC errors, RDC errors are very expensive in identification and debugging. Same as with CDC, LINT tools are capable to efficiently locate and fix RDC errors at early design stages.

Boosting Productivity with Unit Linting - The Unit Linting concept allows designer to verify designs-under-development that are not ready yet to be elaborated in the hierarchical structures. Essentially, Unit Linting complements the compiler in finding various design issues such as coding inefficiencies and potential simulation-to-synthesis mismatches. Since Unit Linting is intended to be run during code development, it allows designers to find and fix important design errors at the earliest stages of the design process, therefore boosting productivity.

Solving a Sudoku Game with BinCNN - This demo utilizes BinCNN machine learning algorithm to solve a Sudoku game. A USB camera and TySOM-3-ZU7EV board is used in this project. BinCNN is a neural network trained for recognizing numbers between 1 to 9. In this project, the ARM processor grabs the images from the camera and processes them by resizing, filtering and distinguishing the empty and non-empty boxes. Then, the non-empty boxes are passed to BinCNN. It receives the images and recognizes the number and the position of the box. The results are passed to the Sudoku solver IP inside FPGA to solve the puzzle. At the end, the results are written on the primary image and shown on the screen.

FPGA-based Implementation of ADAS Bird’s Eye View (Embedded Vision)- The computation-intensive functions of the ADAS Bird’s Eye View (Surround View) application are accelerated and implemented in the FPGA to achieve 30 fps. The surrounding views of the car are stitched together to simplify the object detection for the processing system. The solution includes a TySOM-3-ZU7EV board, FMC-ADAS daughter card and 4x blue eagle cameras. In this demo, images from the cameras are captured using the FMC-ADAS and passed to the Zynq device on TySOM-3. The color space conversion, resizing and perspective transportation are done inside FPGA. Then, all the frames are stitched together to provide the bird’s eye view.

Re-configurable Accelerators for HPC Applications - We will showcase a new board HES-XCVU9P-QDR designed to meet standards and requirements of HPC applications. Aldec’s board contains a Xilinx® Virtex™ UltraScale+ XCVU9P FPGA combined with QDR-II+ or DDR4 memory modules and provide high throughput for algorithm acceleration and data processing using the PCIe interface protocol. The PCIe x16 half-length low-profile board is 1U compatible and easily fits into enterprise rack systems for maximum performance density and simple deployment in data centers.

Genome Short Reads Alignment - Aldec to present AccuRA™, a high-performance reconfigurable FPGA accelerator engine for ReneGENE™, offered on Aldec HES-HPC™ for accurate, and ultra-fast big data mapping and alignment of DNA short-reads from the NGS platforms. AccuRA demonstrates a speedup of over ~ 1500+ x compared to standard heuristic aligners in the market like BFAST which was run on an 8-core 3.5 GHz AMD® FX™ processor with a system memory of 16 GB. AccuRA employs a scalable and massively parallel computing and data pipeline, which achieves short read mapping in minimum deterministic time. It offers full alignment coverage of the genome (million to billion bases long), including repeat regions and multi-read alignments.

From Traceability to Reusability - One method to implement reusability is traceability, in which relations and dependencies between requirements, design, test scenarios and verification goals are identified and linked. In this presentation we propose an automated method to implement traceability in the hardware development process in order to achieve reusable requirements, design and verification artifacts.

Generating DO-254 compliant documents for FPGA projects - Developing FPGAs and ASICs for DO-254 compliance entails that applicants submit extensive professional documents and artifacts to the designated certification authority. The documents must also include project data like design and verification artifacts which usually are scattered in many different documents. In this presentation we will show how to generate DO-254 compliant documents contained valid and actual project data.