Events Schedule

Recorded Events
Date Event Type Location Action
Aug 15, 2024 Why Should Our Team be Using VHDL + OSVVM for Verification? (US) Webinar Online Register
Aug 15, 2024 Why Should Our Team be Using VHDL + OSVVM for Verification? (EU) Webinar Online Register
Aug 21, 2024 What can you do with SystemVerilog verification? Webinar Tokyo, Japan Register
Aug 22, 2024 Using OSVVM’s AXI4 Verification Components

Part 1 - Creating the AXI4 Testbench / Test Harness (EU)
Webinar Online Register
Aug 22, 2024 Using OSVVM’s AXI4 Verification Components

Part 1 - Creating the AXI4 Testbench / Test Harness (US)
Webinar Online Register
Aug 28, 2024 Using SVA for Requirements-Based Verification of Safety-Critical FPGA Designs Webinar Tokyo, Japan Register
Aug 29, 2024 DVCon Japan 2024 Industry Event Tokyo, Japan More Info
Sep 05, 2024 Using OSVVM’s AXI4 Verification Components

Part 2 - Writing Tests and Configuring the AXI4 VCs (US)
Webinar Online Register
Sep 05, 2024 Using OSVVM’s AXI4 Verification Components

Part 2: Writing Tests and Configuring the AXI4 VCs (EU)
Webinar Online Register
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