Riviera-PRO Configurations

ALDEC simulators provide comprehensive support of the IEEE 1076-1993 Standard, IEEE 1076™-2002 VHDL standard and majority of just published IEEE 1076™-2008 Standard.More >>

ALDEC simulators provide full support of the IEEE 1364-2005 Standard. To enable simulation of a large variety of Verilog designs, both legacy and new, ALDEC simulators can be set to work in Verilog ’95, 2001 and 2005 modes.More >>

SystemVerilog is a set of extensions to the Verilog HDL that allow higher level of modeling and efficient verification of large digital systems.More >>

SystemC is a C library that extends C to enable hardware modeling. Although strictly a C class library, SystemC is sometimes viewed as being a language in its own rightMore >>

Riviera-PRO supports SystemVerilog (IEEE Std. 1800™-2012) in three areas: hardware description extensions, assertions and advanced verification.More >>

Verification Libraries (OSVVM, UVVM, cocotb)More >>

The IP-XACT format is widely used for easier packaging and reusing IPs.More >>

Universal Verification Methodology (UVM)More >>

The HDL Editor is a text editor designed for editing an HDL source code. It is tightly integrated with the compiler and simulator to enable debugging capabilities.More >>

UVM Generator: The UVM Generator is a tool that helps create a new UVM environment. Register Model Generator: Register generator is a command line tool allowing the user to generate register models automatically for design and verification purposes.More >>

The HDL Editor allows using code autocomplete for all the languages supported by Riviera-PRO. More >>

Riviera-PRO’s HDL Editor performs an automatic on-the-fly analysis while source code is being edited:More >>

The Design Manager is a tool that allows you to view and manage workspaces, attached designs and their resources like HDL source files, waveform files, macros, code coverage and profiler results with a single mouse click.More >>

With large number of windows available in Riviera-PRO, keeping all of them open simultaneously is not feasible and frequent reconfiguring of GUI is tedious.More >>

Riviera-PRO enables project task management based on the Tasks window. The window is an easy to use tool which represents current list of tasks assigned within a project.More >>

Aldec simulators support several scripting methods varying in the level of abstraction and possible applications. More >>

Simulations can be stopped on a breakpoint. Aldec supports both breakpoints in the source code as well as signal breakpoints.More >>

Stepping through source code is one of the most common debugging procedures. Stepping is executing code one line at a timeMore >>

The Accelerated Waveform Viewer is a high performance tool for graphical presentation of simulation data stored in a binary simulation database (*.asdb).More >>

The Signal Agent in VHDL allows monitoring and driving VHDL signals from any VHDL block.More >>

Post Simulation Debug is an advanced feature that allows users to observe the simulation results after the simulation has been finished.More >>

In large designs where multiple signals must be observed during simulation, keeping them in one waveform window is inconvenient: since all signals cannot fit in one window, frequent scrolling is required to get to the desired waveform data.More >>

The Compare Waveforms option compares waveforms displayed in the Waveform window with pattern waveforms from a specific waveform file.More >>

The Memory Viewer is a debugging tool that has been designed to display memory objects defined in an active design.More >>

Plot window is a debugging tool that visually represents large arrays of data. It support four different plot types and enables HDL design and verification engineers to not only visualize large data sets but also visualize and analyze relations between any objects in their design with no additional programming required.More >>

Image windows is a debugging tool that displays image stored in a memory-like simulation object (Image) or visualizes simulation object values by a color (Color Map).More >>

FSM window is debugging tool that allows observing finite state machine operations. This tool generates a transition graph of any simulation object and shows transitions among object states (or signal values). More >>

The Classes window is a debugging tool that presents SystemVerilog classes in the form of a hierarchical tree view.More >>

Riviera-PRO allows simultaneous and seamless debugging of pure SystemC designs and mixed HDL-SystemC in a single environment.More >>

Design and verification engineers who implemented assertions and covers in their project can observe their behavior during regular simulation and debugging in multiple windows.More >>

Riviera-PRO output FSDB files that work with Synopsys (formely SpringSoft) Verdi and legacy Debussy debuggers. Riviera-PRO work with Synopsys products in post-processing mode(PSD).More >>

X-Trace helps you quickly identify the cause of unexpected values by reporting information on changes from valid to unknown, uninitialized, or user-defined values in the simulated model.More >>

The Dataflow window is a powerful tool that allows designers to explore the connectivity of an active design and analyze dataflow among instances, concurrent statements, signals, nets, and registers during simulation.More >>

UVM Graph is a tool that presents architecture of the UVM-based testbenches in a graphical format.More >>

Most ALDEC simulator configurations support mixed (VHDL and Verilog) designs, but single language (VHDL-only or Verilog-only) configurations are also available.More >>

The Verilog PLI (Programming Language Interface) and VPI (Verilog Procedural Interface) provide a standard mechanism to access and modify data in a simulated Verilog model.More >>

The VHPI interface provides a standard means to access data in VHDL models elaborated in Active-HDL and Riviera-PRO.More >>

DPI, or the Direct Programming Interface, is the next generation interface between SystemVerilog code and foreign C/C++ code.More >>

The VCD (Value Change Dump) file format is specified in the IEEE Std. 1364-1995 standard. The VCD file is an ASCII file containing header information, variable definitions, and variable value changes.More >>

With incremental compilation, small change in one of many design sources does not require recompilation of the entire design. Compilers working in incremental mode can ignore not only files that were not changed, but also areas of larger files that were not modified.More >>

Compilers can utilize newer workstations with multiple processors/processor cores to simultaneously translate different parts of the design, significantly reducing compilation times.More >>

Library protection offers four security levels when compiled models are distributed in the form of library files without releasing their source code.More >>

IEEE 1735™ Interoperable EncryptionMore >>

Using standard design source encryption is a much easier form of managing IP creation and delivery than any kind of binary file encryption. Riviera-PRO supports standard methodology introduced in IEEE Std. 1076-2008. More >>

Using standard design source encryption is a much easier form of managing IP creation and delivery than any kind of binary file encryption. Riviera-PRO supports standard methodology introduced in IEEE Std. 1364-2005. More >>

Aldec simulators support the SecureIP methodology of IP delivery implemented in Xilinx tools.More >>

The ability for the simulator to run at 64-bit bus throughput application speeds and utilize extended memory. (Not applicable on Riviera-PRO LV).More >>

The Verilog RTL & Gate performance optimizer accelerates simulation of all types of Verilog designs, including designs with timing, gate-level designs, and designs with predominantly behavioral code. More >>

Dynamic Object Tracing refers to advanced capability of Riviera-PRO framework that enables representing SystemVerilog class objects in Waveform Viewer. More >>

Transaction-Level Visual Debugging refers to advanced capability of the Waveform Viewer that enables representing simulation data at a higher level of abstraction. More >>

The Profiler identifies design units or code sections that put the greatest strain on the simulator. This information is valuable for optimizing the simulation environment and improving performance.More >>

Due to the complexity of contemporary designs, there is a need for extensive testing of new products. Server Farm Manager (SFM) shifts the regression paradigm and provides not only simulation technology but also a tool for automatic management of thousands of parallel simulations. More >>

Acceleration speeds up verification by co-simulating HDL code and portions of the design pushed into hardware (mainly well tested blocks or IP blocks). Emulation allows in-hardware simulation and extensive debugging of large systems that will eventually work on different platform.More >>

Code Coverage is a debugging tool that aids the verification process.More >>

Specification of properties and their use in assertions and functional coverage is the essential element of designing modern systems and their verification algorithms.More >>

Functional Coverage can provide information about the quality of the design verification process.More >>

Keysight SystemVue co-simulation interface reduces development time and effort by enabling continuous test verification through the system and hardware development process.More >>

The Simulink Interface simplifies verification of hardware designs by providing robust visualization and analysis toolsets.More >>

Aldec simulators integrate The MathWorks' intuitive MATLAB language and a technical computing environment.More >>

Aldec QEMU Bridge it is transaction accurate bridge that allows full SoC co-simulation between the Programmable Logic (PL) system and Processing System (PS)More >>

Aldec® ALINT-PRO™ is a design verification solution for RTL code written in VHDL, Verilog, and SystemVerilog. The solution performs static analysis based on RTL and SDC™ source files uncovering critical design issues early in the design cycle.More >>

Set of rules that should be used to improve design compliance with DO-254.More >>

Dual-language rule library driven by customer requests.More >>

Rules for SystemVerilog RTL design subset that cover new varieties of harmful RTL defects related to new language constructs.More >>

Language-independent rules for CDC and RDC verification aimed to avoid metastability issues in complex designs.More >>

The most comprehensive rule library covering large variety of topics.More >>

Dual-language rule library automates the methodology for effective design reuse and verification.More >>

The network floating configuration (multiple users) is based on a license started on a remote machine (license server) running on the Windows or Linux platform.More >>

One Year Time Based License (TBL) grants a designer a license to use the product for a period of one year. A 1 year support contract is included with the purchase of TBL license.More >>

A perpetual license is a license with no expiration date. A 1 year support contract is included with the purchase of perpetual license.More >>

Linux x86/x86_64 support.More >>

Builds are tested on all the latest platforms to ensure correct operation on users' workstations.More >>