Universal Verification Methodology (UVM)Category : Supported Standards Universal Verification Methodology (UVM) is an open source SystemVerilog library allowing creation of flexible, reusable verification components and assembling powerful test environments utilizing constrained random stimulus generation and functional coverage methodologies. UVM is a combined effort of designers and tool vendors, based on the successful OVM and VMM methodologies. Its main promise is to improve testbench reuse, make verification code more portable and create new market for universal, high-quality Verification IP (Intellectual Property). Verification Libraries (UVM and OVM)
