Open Source VHDL Verification Methodology (OSVVM) OSVVM is a suite of libraries designed to streamline your VHDL entire verification process, boosting productivity and reducing development time. Each library provides independent capabilities, allowing selective adoption and a learn-as-you-go approach. Whether using directed or random testing, OSVVM facilitates writing concise and readable test cases for both unit/RTL tests and complex FPGA and ASIC tests. OSVVM provides VHDL with verification capabilities that rival SystemVerilog + UVM. These include transaction-level modeling, verification components, co-simulation with software, randomized test generation, self-checking test support, verification data structures, comprehensive test reporting in HTML and text, and synchronization primitives. With OSVVM and a good team lead, any VHDL engineer can do verification – and have fun doing it. The latest OSVVM library is included in the installation of the latest versions of Active-HDL and Riviera-PRO. Primary Use Case OSVVM allows any VHDL engineer to write VHDL testbenches and test cases for both simple unit/RTL level tests and complex, randomized full chip or system level tests. Benefits Developed by VHDL experts who actively contribute to VHDL standards development, OSVVM leverages their expertise to provide the following advanced verification capabilities and benefits: Scalable Transaction-Based Framework: OSVVM’s transaction-based framework, which is based on verification components, is adaptable to a wide range of verification tasks, from unit/RTL testing to full chip/system-level verification. Standardized Transaction API and Interface: The OSVVM Model Independent Transaction (MIT) library defines a standardized transaction API (procedures read, write, send, get, etc.) and interface (a record) for streaming and address bus type interfaces. Streamlined Verification Component (VC) Development: Using the MIT library enables any VHDL engineer to create verification components as effortlessly as writing procedures. Readable and Reviewable Test Cases: Using the MIT transaction API simplifies and abstracts test case development, enabling any VHDL engineer to write test cases that the entire team understands, including software and system engineers. Unmatched Test Reporting: OSVVM automatically generates HTML-based test suite reports, test case reports, and logs that facilitate debugging and detailed test artifact collection. OSVVM functional coverage reports rival those produced by SystemVerilog vendor tools. Advanced Capabilities for Comprehensive Verification: OSVVM’s verification capabilities include Constrained Random, Functional Coverage, Intelligent Coverage Randomization, Scoreboards, FIFOs, Memory Models, Requirements Tracking, error logging and reporting, message filtering, and synchronization primitives, all of which are easy to use and work like built-in language features. Directed or Random Test Cases: Using the MIT Transaction API allows you to freely mix directed, constrained random, and intelligent coverage randomization test methods. Directed tests offer precise control over test scenarios, while random tests introduce variability that facilitates covering hard to reach or unexpected edge cases. Simplified Self-Checking: OSVVM’s extensive error checkers and Scoreboards produce detailed test pass/fail messages and simplify creating self-checking tests. Debug Faster: OSVVM’s extensive reports, error messages, and log messages simplify both debugging and recording test artifacts (evidence that good things happened). Requirements Tracking: OSVVM generates an HTML requirements summary for each test case that has requirements. In addition, OSVVM generates a merged HTML requirements summary when any test in a build (a set of tests) has requirements. Co-simulation Capability for Hardware-Software Integration: OSVVM's co-simulation capability facilitates the execution of software (C++) within a hardware simulation environment. This co-simulation interface supports all MIT-based verification components, including the ones you write. Testbench Automation / Continuous Integration (CI/CD): OSVVM seamlessly integrates with continuous integration tools and produces JUnit XML test suite reports. Universal Scripting API for Cross-Simulator Compatibility: OSVVM’s scripting API (a layer on top of TCL) supports Aldec Riviera-PRO and Active-HDL and a wide range of VHDL simulators. This ensures that you can use “One script to run them all”. Simplified Code Coverage Integration: OSVVM scripting provides a simplified mechanism to enable simulator-based code coverage and generate merged code coverage reports for a suite of test cases. Extensive Verification Component Library: OSVVM provides a comprehensive verification component library with components for AXI (Full and Lite), AXI Stream, xMII (Ethernet), UART, and DPRam. Increased Reuse and Productivity: OSVVM’s modular approach provides numerous opportunities for increased productivity and reuse, from using OSVVM’s libraries full of capabilities, to reusing sequences of transactions to test a similar interface, to reusing VCs and test cases at different levels of testing, to reusing VCs on different projects. Any VHDL Engineer can do OSVVM: OSVVM verification components and test cases can be written by any VHDL engineer. If necessary, verification components can be developed by outside resources without sharing sensitive design information. A Viable Alternative to SystemVerilog + UVM: OSVVM stands as a powerful rival to the verification capabilities of SystemVerilog + UVM, while offering a simpler learning curve and ease of use. OSVVM is free open source released under APACHE 2.0 license: You can find OSVVM on GitHub and IEEE Open Source. We accept issues and pull requests on GitHub. Join us. Webinar Video: Better FPGA Verification with VHDL Part 1 - OSVVM: Leading Edge Verification for the VHDL Community Looking to improve your VHDL FPGA verification methodology? OSVVM is an ideal solution. It has all the pieces needed for verification. There is no new language to learn. It is simple, powerful, and concise. Also, each piece can be used separately, so you can learn and adopt pieces as you need them. In part 1 of this webinar series, we provide a broad overview of OSVVM's capabilities and discuss the OSVVM verification framework, verification components, self-checking tests made easy, simplifying test printing with OSVVM logs, constrained random tests, scoreboards, functional coverage, and intelligent coverage random, protocol and parameter checks, test watch dog timers and test reporting. Other Webinar Recordings for OSVVM Better FPGA Verification with VHDL Part 2: Faster than Lite Verification Component Development with OSVVM Better FPGA Verification with VHDL Part 3: OSVVM's Test Reports and Simulator Independent Scripting Better FPGA Verification with VHDL Part 4: Advances in OSVVM's Verification Data Structures Additional Links OSVVM Forum: https://osvvm.org/ OsvvmLibraries using Git: https://github.com/OSVVM/OsvvmLibraries OsvvmLibraries as a Zip: https://osvvm.org/downloads OSVVM Documentation: https://osvvm.github.io/ OSVVM Reports: https://osvvm.github.io/Overview/Osvvm3Reports.html OSVVM Classes: https://synthworks.com/vhdl_testbench_verification.htm
