Universal VHDL Verification Methodology (UVVM)

UVVM is an open source VHDL verification library and methodology, available on both Github and IEEE Standards Association Open, and is developed in cooperation with the European Space Agency (ESA). The latest UVVM library is included in the installation of the latest versions of Active-HDL and Riviera-PRO.

A major advantage of using this VHDL-based approach is that you can use the design language you already know and add, step-by-step, the functionality you need for your specific testbench. Moreover, you only need VHDL, thus resulting in simpler, faster and cheaper verification. UVVM works with any VHDL 2008 compatible simulator and may also be used for ASIC verification – even for a Verilog design under test (DUT).

UVVM is seen as “UVM for VHDL”, but with a far lower user threshold, and was made to target the following for your testbench:

• Overview and Readability
• Modifiability, Maintainability and Extensibility
• Debuggability
• Reusability

UVVM has lots of interface models for accessing various interfaces. These are provided as bus functional model (BFM) procedures, for simple usage, and as VHDL verification components (VVCs) for more advanced verification. These interface models allow you to write high level transactions (procedures) to create easily understandable test cases. 

The VVCs of UVVM provide unique functionality that allows more efficient verification in a single project, and even more so for reuse at all levels. Features include:

• All DUT interfaces can be controlled from a single test sequencer
• Interface activity can be easily skewed with respect to each other
• Split transaction and out-of-order interfaces may be handled in a very structured manner
• Common commands to control general VVC features
• May use Broadcast and Multicast for more efficient VVC handling
• Full encapsulation and thus directly reusable
• Standardised interfaces and functionality so that VVCs from different users will work together

UVVM focuses on simplicity where it matters, and software and hardware developers alike can easily read and write UVVM test cases. Also, the methodology is very well documented with description, syntax and examples. You can also find demo and maintenance testbenches (inside UVVM Supplementary) for any functionality.

UVVM is a verification methodology that targets cycle-related corner cases, which are often very error prone, and the inventor the methodology, Espen Tallaksen of EmLogic (Norway), is still the project manager and chief architect.

Primary Use Case

UVVM has been targeted to improve VHDL testbench readability, overview and maintainability. Simple DUTs can be verified using the simple UVVM Utility Library and BFMs, whereas very structured UVVM testbench architectures can be made to verify complex DUTs in a very simple way, thus significantly improving efficiency and quality.

Benefits

UVVM provides the following functionality:

• Basic test case support and infrastructure with procedures for checking values, checking stability, waiting for values or change, pulse and clock generation, flag/semaphore/barrier handling, alert handling, logging, verbosity control, string support, normalization, etc.
  • Very low user threshold.
  • Reduces test case code size significantly while at the same time improving readability and quality.
• Bus functional models (BFMs) and Verification Components (VVCs) for:
  • AXI4-lite and AXI4-stream.
  • Avalon MM and Avalon-stream.
  • SPI, I2C, SBI, UART, GPIO, and Wishbone.
  • GMII and RGMII.
  • Ethernet.
• Lego-like connection of verification components, hence:
  • No connection is needed to the test case.
  • Test cases can thus be simplified.
  • Test harness can be modified without the need for signal or port changes.
• Simple, advanced, and optimised randomisation.
• Functional coverage.
• Specification coverage / Requirement traceability.
• Generic Scoreboards.
• Error Injection.
• Protocol checker capabilities.
• Monitor example.
• Watchdogs.
• Transaction level modelling / High level transactions.
• Transaction info access.
• Local sequencers.
• Activity registration and Completion detection.
• Hierarchical Verification components.
• FIFOs and Queues.
• No lock-in. You can pick just a single functionality - e.g. await_value() - specification coverage or an AXI-stream VVC.
• Works with any legacy testbench.

Webinar Video: Enhancing the Simulation Testbench for VHDL-based FPGA Designs (Part 1) Basic Testbench for a Simple DUT

Functional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series, we will present a step-by-step approach on how to architect a testbench - progressing from basic to advanced techniques. We will first use a simple DUT then go to a more complex DUT with simultaneous activities on multiple interfaces.

In part 1 of this webinar series, we show you how to verify a relatively simple DUT with low- to mid-quality requirements using a basic testbench without using any verification framework. We also discuss the elements of a basic testbench infrastructure, show examples of how to create self-checking testbenches with verbosity and alert control, and introduce the use of basic BFMs to speed up verification and debugging. We then introduce UVVM and show you how to use it to verify a simple DUT.

Other Webinar Recordings for UVVM

• Enhancing the Simulation Testbench for VHDL-based FPGA Designs (Part 2) Advanced Testbench for a Simple DUT
• Enhancing the Simulation Testbench for VHDL-based FPGA Designs (Part 3) Advanced Testbench for a Complex DUT

Additional Links

• https://github.com/UVVM/UVVM
• https://uvvm.github.io
• https://forum.uvvm.org/
• https://emlogic.no/uvvm/
• https://github.com/HDLUtils/hdlregression