Verification IP Today’s ASIC and SoC designs contain many complex industry standard interfaces to communicate with external devices (like USB, PCIe etc.) or standard buses (like AHB, AXI etc.). During design verification process these interfaces are also used to connect with the test environment (testbench). This connection is realized via modules called Verification IP (VIP). Verification IP (VIP) is a special kind of IP Core that combines function of Bus Functional Model (BFM) of a given interface with Test Harness features for use in the testbench. Very important factor that should be considered when choosing or developing VIP is their reuse in emulation as simulation becomes inefficient when the design grows. For this reason well designed VIP should be based on co-emulation industry standard, namely the Accellera’s SCE-MI. VIPs can serve different purposes and based on this we differentiate three main categories. Transactors are modules that establish communication channel between software part of testbench (HDL Simulator, Virtual Platform, etc.) and the design. Transactor’s communication channel is implemented with use of high level messages that are translated by the BFM into correct standard interface protocol signaling. The testbench can inject bus transfers or respond to transfer requests using transactor. Comprehensive VIP should be configurable and also provide errors injection and handling functionality. Monitors are conceptually similar to Transactors and they are used in soft-testbench but have only a monitoring/read-only capability. Their BFM can capture and recognize a standard interface signaling protocol and translate it to higher level messages that can be collected and send to the testbench for analysis or debugging purposes. Speed Adapters are used to connect design running in emulator with external hardware i.e. real devices. Their primary functionality is to synchronize emulation clock domain with real devices that usually have higher clock rates. Complex interfaces usually require proper synchronization in the protocol layer. Developing a VIP for the complex interface like USB or PCIe is not a trivial task, so in order to save on schedule time and reduce project risks it is often decided to reuse third party VIPs instead of developing own ones. Thus availability of reliable and proven VIP is a key to successful design verification and tape-out. Aldec’s expertise in various verification techniques including simulation, emulation, prototyping and commitment to solve real customer’s problems resulted in developing a number of VIPs for industry standard interfaces like USB, PCIe, AXI, AHB, OCB, Gb Ethernet and others. Aldec’s VIPs are available in all three categories Transactors, Monitors and Speed Adapters. They provide interfaces in System Verilog or C++ and so can be used in any kind of verification environment including simulation with UVM testbench or SystemC based Virtual Platform. Due to strict adherence to Accellera’s SCE-MI standard, Aldec’s transactors and monitors can be used with design that is either simulated or emulated. To check for availability of a given VIP check the VIP/IP Core product page and search the database selecting VIP type. If you do not find required VIP or proper configuration please request information about VIP services. We’ll use our experience to develop reliable VIP and deliver it on time. Application example with Aldec’s VIP used for UVM Simulation Acceleration and Co-emulation.
