« Prev | Next » Using Cocotb for design re-use and randomized testing in Riviera-PRO Introduction This application note provides information on how to use cocotb, a python based verification environment, to run randomized verification using Riviera-PRO. To get started, first let us understand the basics: What is Cocotb? Cocotb is a CO-routine based CO-simulation Testbench environment for verifying VHDL/Verilog RTL using Python. It is an open-source environment and hosted on Github. Cocotb can use Riviera-PRO simulator to simulate the RTL. It basically helps in the testing process and makes it comfortable, especially for people who are not very familiar with the HDL concept of verification. It uses the same design-reuse and functional verification concepts like UVM, however is implemented in Python. Hardware Description Languages such as VHDL, Verilog and System Verilog are used for the synthesizable designs only. Cocotb also has a built in support for integrating with the Jenkins continuous integration system. Why Cocotb? Cocotb does not require any additional RTL code. The Design Under Test is instantiated as the top level in the simulator. Stimulus is applied onto the inputs to the DUT and outputs are monitored using Python. Considering the fact that it does not require to know HDLs, it can be a boon to people inexperienced with it. Also, Python is an object oriented scripting language. Additionally Python has garbage collection memory system which makes the program execution very fast and easy to understand. Python is much simpler to be understood and that leads to faster development and less overhead. Thus, Cocotb has some serious benefits to be considered over HDLs testing methodologies. To get started with Cocotb, Users must meet following requirements: Python 2.6+ Python Dev Packages GCC and Associated development Packages. GNU make Riviera-PRO Simulator For further download related information depending upon your Operating system, please follow the link below: http://cocotb.readthedocs.io/en/latest/quickstart.html Working with Cocotb As part of Cocotb, test-benches does not require any RTL code which we usually do using Verilog/System Verilog. The Design-Under-Test is instantiated as top level module file in the simulator. Further it drives stimulus to the inputs of the DUT and monitors the outputs directly. Creating Cocotb Test Cocotb tests are written in Python. Typically as part of a test-bench, we need to provide inputs such as Clock and reset. Assuming we have such top level ports called clk and rst, we can create the following file:- import cocotb from cocotb.triggers import Timer @cocotb.test() def practice_test(my_design): my_design._log.info("Creating test") for cycle in range(100): my_design.clk = 0 yield Timer(1000) my_design.clk = 1 yield Timer(1000) Above example drives a clock signal onto the clk port of the top level. rst = my_design.rst #referencing to the rst signal at top level. rst.value = 1 #Assigns value 1 to signal rst. Above example shows how to reference a particular signal at top level and how to assign value to a signal. Apart from that, testbenches are built using Coroutines. The simulation is paused while the coroutine is executing. For more information on how Cocotb works, please refer to the following link for Quickstart Guide: http://cocotb.readthedocs.io/en/latest/quickstart.html Next, we will see the working of Cocotb with Riviera-PRO. Working of Cocotb with Riviera-PRO Once you download the Cocotb from the provided link above, make sure you have required python version on your computer. If not, Python can be downloaded from https://www.python.org . Make sure the python installation path has been added to System PATH variable. Next, run the installer . Cocotb install comes with inbuilt examples. This application note contains information based on one of those examples. The endian swapper example includes both VHDL and Verilog RTL implementation. Make sure that you are in the example directory that you are trying to use. The Cocotb testbench can execute against the VHDL implementation using the following command. make SIM=aldec TOPLEVEL_LANG=vhdl Linux Shell Terminal On giving the command provided above, the installer will invoke the make file available in the endian_swapper example directory and simulation execution will take place in batch mode. Simulation Execution in batch mode Waveform Viewer Riviera-PRO Similarly, Cocotb execution can take place with the help of GUI version of Riviera-PRO as well. Command to invoke Riviera-PRO GUI When the command-line includes command invoking Riviera-PRO GUI as well as written above, Riviera-PRO GUI invokes. Script in GUI mode As the GUI invokes, make sure you are in the right directory and execute the script. Similar results as found using batch mode could be seen with the help of GUI mode as well. Advantages of Cocotb Cocotb has built-in support for integrating with the Jenkins Continuous Integration System. The main motive behind the creation of Cocotb is to lower the overhead of creating tests. It automatically discovers tests so that no additional step is required to add a test to a regression. Verification language is Python which has several advantages over System Verilog/Verilog and UVM. Python has a plethora of frameworks that makes programming very flexible. It gives rise to quick development by using less code. Easy to learn and fast to decode. Object Oriented Programming driven framework. It is supported on multiple systems and platforms. References [1] Cocotb Documentation http://cocotb.readthedocs.io/en/latest/index.html [2] Potential Ventures Official Website http://potential.ventures/cocotb/ Disclaimer Many of the text in this application note were extracted from the referenced sources regarding the open-source tools support they provide. The intention of this application note is to consolidate and organize the data and present a simplified tool flow for the benefit of Aldec users. Previous article Next article
