Starting Riviera-PRO as Default Simulator in Xilinx Vivado

Introduction

This document describes how to start the Riviera-PRO simulator from Xilinx Vivado™ to run behavioral and timing simulations. It applies to all Vivado releases starting from 2017.4 up to the latest edition and has been verified on Riviera-PRO 2023.04, Xilinx Vivado 2023.1, and the Riviera-PRO Simulator 1.33 add-on to Vivado. This integration allows users to run VHDL, Verilog, SystemC, Mixed, and SystemVerilog simulations using Riviera-PRO as the default simulator.

Setting up Integration Options

Make sure that the latest version of the Riviera-PRO Simulator plug-in is already installed.
Set the path to the Riviera-PRO installation directory in the 3rd Party Simulators category by going to Tools | Settings | 3rd Party Simulators. Alternatively, add the Riviera-PRO installation directory to the PATH environment variable. The settings from the Vivado environment take precedence over the path specified in the environment variable.

NOTE: If Vivado is already running while you modify the PATH environment variable, then you will have to restart Vivado to have your new PATH variable effective inside Vivado.

Installing Xilinx libraries in Riviera-PRO

In order to run the simulation successfully, depending on the design, VHDL, Verilog, or SystemC simulation libraries for the respective Xilinx Vivado version may have to be installed in Riviera-PRO. You can check which libraries are currently installed in your Riviera-PRO version using the Libraries window. The window can be started with the Libraries button from the Design Management toolbar or with the Libraries option from the View | Design Management menu. Libraries have to be compiled for the Riviera-PRO version you are using for simulation.

You can obtain libraries in multiple ways:

You can compile Xilinx libraries from sources with the Compile Simulation Libraries option from the Vivado Tools menu or the compile_simlib -simulator riviera command.

NOTE: After generating the compiled libraries from Xilinx, they have to be attached to Riviera-PRO environment. For more information refer to Compiling Xilinx Vivado Simulation Libraries for Riviera-PRO.

You can also install precompiled libraries:
If you have received a web link to download Riviera-PRO, on the same page you will find the links to download Xilinx libraries.
At any time you can visit the Update Center to download the latest Xilinx libraries at https://www.aldec.com/en/downloads.

Here is the typical sequence you would like to follow to run Riviera-PRO from Vivado:

Create or Open a project in Xilinx Vivado Project Manager.
Select the Settings tab from the Flow Navigator pane.
Under the Simulation category of the Settings window, change the Target Simulator to Riviera-PRO Simulator.
The libraries used in the project should be specified either in the Riviera-PRO or Vivado environments. For details, refer to Compiling Xilinx Vivado Simulation Libraries for Riviera-PRO.
Here under the Compilation tab, you can enable a range of the Verilog and VHDL compiler features such as the coverage analysis and debug mode or assign values to generics/parameters. The generics/parameters can be set in the Generics/Parameters options field whereas the features can be selected from the list of available compiler options. The options present in this tab as well as the options from the Elaboration and Simulation tabs are described in detail in Riviera-PRO Simulator Options in Vivado.

NOTE: You may need to select the riviera.compile.vhdl_relax check box that relaxes some LRM requirements when compiling VHDL files.
Under the Elaboration and Simulation tabs you can set simulation related arguments e.g. logging all signals to simulation database, accessing signals for waveform, simulation run time.
Once all options are set according to your requirements, click OK.

NOTE: If a version of Riviera-PRO was updated between subsequent simulation runs, you should clear the Enable incremental compilation option available in the Advanced tab of the Simulation category to remove the files compiled with previous version of Riviera-PRO.
Now, click on the Run Simulation item in the Flow Navigator pane and select the type of simulation you want to run. This will run the simulation in the GUI mode.

Alternatively, you can run the simulation in the Console mode. To do so, type the following commands in the Vivado Tcl Console window:

launch_simulation -batch -install_path <path>
Vivado generates DO macro scripts for compilation and simulation based upon the settings you provided in the above steps and stores them in the <project_dir>\<project_name>.sim\<simulation_set>\<simulation_type>\riviera directory.
- The compilation macro (<name>_compile.do) sets up the working libraries to which the design will be compiled, maps the Xilinx Vivado libraries, and runs the compilation with the options specified in Project Settings | Simulation | Compilation.
- The simulation macro (<name>_simulation.do) initializes and runs the simulation session while recording the signal history to the simulation database (ASDB).
The Aldec's compiler executes the compilation macro in the Console regardless of the selected mode. The compiler output is redirected to the Vivado Tcl Console window.
If compilation is finished successfully, Riviera-PRO is launched and the simulation macro is executed. The macro initializes and runs the simulation session while recording the signal history to the simulation database (ASDB). In the GUI mode, the history of signals is presented in the Waveform Viewer when the simulation is completed. At that point, you can navigate through the history of the Console window using the arrow keys and relaunch any command from the simulation macro. To browse the design sources, use the Show Source option from the context menu of the design units that can be inspected after expanding the library items in the Library window. In the Batch mode in turn, the simulator output is redirected to Vivado Tcl Console and Riviera-PRO is closed after simulation completion.

export_simulation command

The export_simulation command allows you to export the compilation and simulation macros generated by Vivado to the directory specified with the -run_dir argument. The macro to be exported is denoted with the -mode and -type arguments.

Syntax

tclapp::aldec::riviera::export_simulation -run_dir [-lib_map_path] [-mode] [-type] [-quiet] [-verbose]

Arguments

-run_dir: Specifies the directory to which the macros selected with the -mode and -type arguments will be exported.
-lib_map_path: Specifies the directory containing the precompiled simulation library.
-mode: Sets the simulation mode. The following modes are allowed: Behavioral, Post-synthesis, and Post-implementation that can be selected with the behavioral, post-synthesis, and post-implementation parameters, respectively.
-type: Specifies the netlist type. The allowed values are functional and timing. This argument is only applicable when the selected simulation mode is Post-synthesis or Post-implementation (post-synthesis or post-implementation passed to -mode).
-quiet: Suspends displaying of error messages reported by the command.
-verbose: Suspends limiting of messages displayed in the console during the command execution.