Performing Functional Simulation of the system created with Platform Designer in Active-HDL

Introduction

This document describes the steps required to run functional simulation of an Intel Platform Designer project (formerly Qsys) in Active-HDL. The Platform Designer System Design Tutorial is used to demonstrate the flow.

Requirements and Limitations

This application note assumes the following:

You have the following software installed and licensed:
- Intel Quartus® Prime Pro 23 or later and all necessary devices from Intel
- Active-HDL 15 or later
You have downloaded the Platform Designer System Design Tutorial example (qsys_pro_tutorial_design_arria_10_17p0.zip) used in this application note. You can download it from the Platform Designer Tutorial Design Example web page.

Generating Design in Platform Designer

Extract the qsys_pro_tutorial_design_arria_10_17p0.zip archive. The C:\ root folder will be used in this document.
Open the Quartus Prime Pro environment.
Click the Open Project button visible on the Home page and pick the A10.qpf file from the main folder of the extracted archive.

Figure 1. The Quartus Prime Pro environment.
Open the Platform Designer by selecting the Platform Designer item from the Tasks pane to the left or the Tools menu.
In the Open System window appearing on the Platform Designer startup, specify the pattern_generator_system.qsys file in the Platform Designer system field available in the System tab. Next, open the design with the Open button.

Figure 2. The Open System window of the Platform Designer.

NOTE: During opening, you will be asked to upgrade all the IP Cores used in the design to the newest versions. Confirm this operation when prompted and save the design after completion.
From the Generate menu of the Main menu, pick the Generate HDL option. This will open the Generation window.

Figure 3. The Platform Designer environment.
In the Synthesis category of the Generation window, pick None in the Create HDL design files for synthesis list and clear all check boxes.
In the Simulation category, pick Verilog from Create simulation model list and ensure that the Riviera-PRO check box is selected.

Figure 4. The Generation window of the Platform Designer.
Click the Generate button to begin the generation process.
Once you generate the simulation models in Platform Designer, the rivierapro_setup.tcl script is generated in the Qsys_Pro_tutorial_design_Arria_10_17p0\pattern_generator_system\sim\aldec folder.

Running Simulation of Platform Designer Design

Open Active-HDL. Change the location to point to the rivierapro_setup.tcl script. Execute the following command from the Console:
```
cd C:\Qsys_Pro_tutorial_design_Arria_10_17p0\pattern_generator_system\sim\aldec
```
Figure 5. Accessing the Platform Designer script in Active-HDL.

Open the rivierapro_setup.tcl script. Execute the following command from the Console:

open -do rivierapro_setup.tcl

This script sets up all necessary environment variables and declares the aliases that compile required libraries, compile design files, and initialize simulation. The script can be executed as is, or you can modify any of the aliases according to your needs. The table below provides the description of the alias commands:

Alias	Description
dev_com	Compiles device library files.
com	Compiles design files.
elab	Elaborates the top level design and initializes simulation. The top level design is defined in the script by the TOP_LEVEL_NAME variable.
elab_debug	Elaborates the top level design with optimizations disabled (-dbg and -o2 are passed to asim) and initializes simulation.
ld	Compiles all libraries and design files, elaborates the top level design, and initializes simulation.
ld_debug	Compiles all libraries and design files, elaborates the top level design, and initializes simulation with optimizations disabled (-dbg and -o2 are passed).

Table 1. Aliases defined in the rivierapro_setup.tcl script.

Navigate to the line of code where the following expression is checked in the condition of the if statement:
```
[ string match "Active" $Aldec ]
```
The QSYS_SIMDIR variable needs to be updated in the statement body so that it pointed to the correct location after loading the design in Active-HDL. The statement should look as follows after applying this modification:
```
if { [ string match "Active" $Aldec ] } {
  scripterconf -tcl
  set QSYS_SIMDIR "./../../../"
  createdesign "$TOP_LEVEL_NAME"  "."
  opendesign "$TOP_LEVEL_NAME"
}
```
Run the script. Execute the following command from the Console:
```
do rivierapro_setup.tcl
```
Once the script is executed, the new design will be created and activated.

Figure 6. The system created with Platform Designer loaded into Active-HDL.
Execute the dev_com command from the Console.

NOTE: If you already have Intel libraries installed, you can skip this step.

This will compile the below libraries:
- altera, altera_ver
- altera_lnsim, altera_lnsim_ver
- altera_mf, altera_mf_ver
- lpm, lpm_ver
- sgate, sgate_ver
- twentynm, twentynm_ver
- twentynm_hip, twentynm_hip_ver
- twentynm_hssi, twentynm_hssi_ver
Execute the com command from the Console. This will compile design source files.
Execute the elab command from the Console. This will initialize the simulation.
Run the simulation by executing the run 40us command from the Console.

Conclusion

Intel Platform Designer projects can be successfully simulated in Active-HDL. To get detailed information about creating a system with Intel Platform Designer, refer to the following link:

https://www.intel.com/content/www/us/en/docs/programmable/683364/18-1/creating-a-system-with.html

If you have difficulty simulating the Platform Designer project in Active-HDL, please contact Aldec Support via customer portal