What is the difference between a Vital Model and Vital Library?

Vital Model defines how ASIC libraries should be specified in Vital-compliant VHDL in order to be simulated in VHDL simulators.

This covers in particular:

• Naming conventions for timing parameters and internal signals, including prefixes for timing parameters, which must be used in the generics specifications.

• How to use the types defined in the Vital _Timing package for specifications of timing parameters;

• Methodology of coding styles;

• Two levels of compliance: level 0 for complex models described at higher level, and level 1, which additionally permits model acceleration.

Vital libraries contain primitives (structural) and other behavioral components adhering to the modeling specifications.