Tutorials

Learn how to use Advanced Dataflow in Riviera-PRO

Learn how to use Assertions in Riviera-PRO

This document will show the process of creating software applications for TySOM development boards by utilizing OpenCV to build an image processing application. OpenCV is an open source computer vision software library that provides the algorithms and functions used for image and video processing.

In this tutorial, you will learn how to use UART to interface the TySOM-1-7Z030 board with other systems. The UART interface enables us to view serial output from the board which can be useful for monitoring. This project has both a hardware and software part.

The Linux operating system is a very popular operating system for embedded applications. Many modern systems including IoT gateways use the Linux OS because of its versatility and support for multiple architectures. The Aldec TySOM platform, which based on the Xilinx Zynq SoC with ARM Cortex processor, can be utilized as an IoT Gateway system. This document describes the process for building an embedded Linux OS for the Aldec TySOM platform using the Analog Devices Linux kernel and Linaro sources for creating Linux File System.

This document describes the process for building an embedded Linux OS for the Aldec TySOM platform using the Yocto project, an open source collaboration project for creating custom Linux-based systems.

Learn how to use Code Coverage in Riviera-PRO

This demo design uses TySOM-3-ZU7EV board to capture the LI_IMX274MIPI camera 4K video through the FMC HPC connector on the board and show it on a screen. LI-IMX274MIPI-FMC is a high-resolution digital camera board. It incorporates a Sony 1/2.5" CMOS digital image sensor with an active imaging pixel array of 3864H x2196V.

This tutorial provides instructions for using the basic features of the Active-HDL simulator. Active-HDL is an integrated environment designed for development and verification of VHDL, Verilog, System Verilog, EDIF, and System C based designs. In this tutorial we use a Sample VHDL design called PressController from the Active-HDL installation to perform design entry and simulation.

This document describes running an HDL simulation using Active-HDL in the batch mode.

This document describes running an HDL simulation using Active-HDL in the GUI mode.

This document describes managing libraries in Active-HDL.

This tutorial explains what compilation and simulation options (switches) must be used to achieve the ultimate VHDL simulation performance.

Active-HDL stores simulation results in a signal database file for easier design management.

The Advanced Dataflow window is a tool that allows you to explore the connectivity of a simulated design and analyze dataflow among instances, concurrent statements, VHDL signals and Verilog nets and variables. Values in the design logic can be traced back to their origin, and forward, to the design outputs.

An HDL code breakpoint can be set in HDL source files that are VHDL, Verilog, and SystemVerilog. A breakpoint can also be set in OVA and PSL code, for example in lines that contain assert or cover statements.

Active-HDL users have access o a rich set of debugging tools that enables quick ways to detect and diagnose design issues.

XTrace tool creates a report with information on unknown values in the simulated model.

Code Coverage aids the verification process by providing information in details whether and how the design is verified or which parts of the design are still untested.