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Riviera-PRO™ addresses verification needs of engineers crafting tomorrow's cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards.

Perspectives are a configured interface which are comprised of different windows and views. When working at different stages of the design flow it can be useful to have different views open, which can be switched to with use of perspectives. Favorites are used to display select tools, macros, or user-defined commands in the interface and different views that are important to have accessible.

The HDL Editor available in Riviera-PRO gives flexibility and provides advanced features to speed up the design process and make debugging easier. It provides shortcuts and tools in every stage of designing. Templates are available to use in the HDL Editor which provides basic constructs in various HDL and gives the option to create templates from code that's already written.

The Outline Viewer available in Riviera-PRO digests VHDL code and breaks it down into it's basic components. It will format and display different components of VHDL code and enable filtering and searching for signals and design objects, making large projects easy to navigate.

Encryption and Secure Sharing is an important aspect for businesses that need to protect their IP against unauthorized utilization. Different levels of IP Encryption and Protection are required when modules are licensed, evaluated or transferred within departments. Riviera-PRO can deliver protected IP in two forms: encrypted source files or precompiled protected libraries.

Using Tasks in your Riviera-PRO Project allows you to track and prioritize assignments inside of a project. Tasks can be assigned to different areas of your project and will help outline the order and how quickly things should be completed.

The Coverage tools available in Riviera-PRO can analyze Code Coverage, Functional Coverage and Toggle Coverage. Control the Coverage of your design using the GUI or through simple script commands. Riviera-PRO will generate HTML and Text reports detailing the Coverage Analysis of your design.

Design Profiling is a feature that will monitor CPU utilization during simulation. Profiling your designs can help identify design units or code sections that put the greatest strain on the simulator and that information can be used to improve the simulation environment and performance of the tool. The information from a profiling session can be displayed using the Profiler Viewer, or you can generate an HTML or CSV report.

Testbench creation is a tedious but necessary process for verifying your designs. Once a design is ready for testing you are able to automatically generate testbenches and VHDL declarations within Riviera-PRO from Verilog, VHDL, or SystemVerilog source files. Use Riviera-PRO to speed up you testbench creation for all of your projects.

The breakpoint management tools available in Riviera-PRO make it easier to debug your design. Breakpoints are used to halt simulation when a condition or state is reached for HDL Code, C Code, Signals, Assertions, or Covers. Breakpoints should be used to create breaks in simulation at specific windows and conditions of testing. They can be helpful to identify functionality of IP or new designs. Riviera-PRO has the capability to set breakpoints and manage them within their corresponding windows.

Aliases and Slices provide the opportunity to associate signal values with strings. They can be identified using mnemonics (nickname), colors, and icons. Slices can take predefined Aliases to divide a signal into all it's separate parts. Using these differentiators can make debugging easier by making large signals easier to separate into their respective parts and can be identified with a color and nickname and icon.

Take a closer look at the Code Coverage feature inside the HDL Editor that exists inside of Riviera-PRO. While running simulations you can use the HDL Editor to track the coverage taking place on your source files for your design. While stepping through testbenches or signal vector stimulus you can watch the design collect coverage statistics. Use the HDL Editor to help complete Code Coverage Analysis and generate your reports.

Take a closer look at the FSM Debug & Coverage tools available for your project inside of Riviera-PRO. Verify FSM functionality and test methodologies using Aldec Proprietary Pragmas, FSM Viewer, FSM List, and easily generated Coverage Reports.

Take a look on how to make use of the UVM Toolbox available in Riviera-PRO for debugging designs and making the most of your verification environment. Use the UVM Viewer, UVM Hierarchy, and UVM Configuration windows to represent UVM architecture and their TLM connections to improve the perspective of the architecture and dataflow. The UVM toolbox features are compatible with UVM 1.2, 1.1d and 1.0p1.

The UVM Register Generator is used to create Register Model files to incorporate into a UVM environment to use the Register Abstraction Layer of UVM. Automatically generating models for the RAL is particularly time saving, considering modern designs can consist of thousands of registers, and coding those by hand would be a long and tedious task, while still being a crucial aspect of the verification of the design. Using a CSV or IP-XACT register description, automatically generate a UVM register model, and quickly integrate it into your UVM environment for faster verification.

Complex hardware/software interactions within system-on-chip devices such as the Xilnx Zynq 7000 and others are requiring more advanced verification tools. Through co-simulation, programmable logic and processing systems can both be tested concurrently and early in the design cycle, allowing for hardware and software team members to work together and correct design bugs early in the verification process. Aldec's QEMU bridge, along with Aldec's Riviera-PRO, allows for this co-simulation, providing an interface between simulator and the QEMU machine emulator which can model the processing system of Zynq devices.

Advanced waveform operations using bookmarks with comments, opening delta cycle to debug race conditions and virtual grouping and virtual arrays for searching through combination of signals, bits.

Basic Waveform operations like browsing using advance modes, finding objects and values, utilizing multiple cursors and sub cursors for time and frequency measuring.

Riviera PRO’s waveform viewer can be utilized for many useful debugging and verification tools, such as comparing datasets. By capturing snapshots of a simulation waveform, you can compare them to observe the differences in simulation results after making changes to the design or testbench. This video will demonstrate how to compare datasets and view the comparisons on a waveform viewer.

Managing your simulation datasets, exploring your design hierarchy and design objects. Loading multiple simulation datasets for debugging and comparison.