1.7 Basics: Compilation and Simulation Active-HDL provides several compilers, respectively for VHDL, Verilog/SystemVerilog, SystemC, and EDIF. Active-HDL automatically employs the compiler appropriate for the type of source file being compiled. When all design units have been successfully compiled, you can begin the simulation. Learn how to specify design settings for compilation (setting up debugging windows, selecting maximum optimization, etc.), how to initialize and run simulations, how to view the simulation results, and how to perform compilation and simulation with scripts.
