2.8 Debugging: FSM Coverage

Active-HDL provides a number of coverage analysis tools to further enhance verification quality of HDL code. Coverage analysis uses ACDB (Aldec Coverage Database) as a unified format of storing different types of coverage data. This video will go into more detail on one of the Code Coverage options: FSM Coverage. FSM Coverage enables users to determine which states and transitions in the state machine diagram have been executed during simulation. To collect the FSM Coverage statistics, the HDL design code has to include SystemVerilog or Aldec proprietary pragmas indicating which constructs represent components of the state machine. The pragmas used in the HDL code are included in additional lines of comments and interpreted by the coverage engine. The FSM Coverage statistics can be stored in the Aldec Coverage Database (ACDB) files and presented in a textual or HTML report along with OSVVM Functional Coverage providing complete structural coverage and functional coverage with test results merging, ranking and analysis.