Play WebinarTitle: HW / SW Co-Verification: Why wait for silicon?Description: Abstract: Traditional design flows postpone HW/SW integration and co-verification until the ASIC prototype is ready. With constantly shrinking time-to-market requirement this is significantly too late. If some HW bugs are identified during SW integration phase then it is impossible to make HW changes. Designers have to find sophisticated SW workarounds in order to avoid costly re-spins. Learn from Aldec how to start HW/SW integration and co-verification much earlier in your design flow along with the extensive debugging capabilities on both sides of HW and SW. Find out how to enable HW and SW design teams collaborate on a whole new level that has never been done before.Signing up for an account is easy. With an Aldec account you'll have easy, one-click access to event registration, support, product downloads, evaluation licenses, recorded webinars, white papers, application notes and other resources. Simply provide your corporate e-mail address below - all account requests are verified and confirmed within 48 hours. If you already have an Aldec account, please Sign In below to download the file. Register Sign In
