Play WebinarTitle: VHDL Intelligent Coverage™ using Open Source - VHDL Verification Methodology (OS-VVM) with Guest Presenter, SynthWorksDescription: At the lowest level, Open Source - VHDL Verification Methodology (OS-VVM), is a set of packages that provide concise and powerful methods to implement functional coverage and randomization. OS-VVM uses these packages to create an intelligent testbench methodology that allows mixing of "Intelligent Coverage™" with directed, algorithmic, file based, or constrained random test approaches. Having an intelligent testbench approach built into the coverage modeling puts OS-VVM a step ahead of other verification methodologies, such as SystemVerilog and UVM. Attend this webinar and learn how to utilize OS-VVM to add functional coverage, Intelligent Coverage, and constrained random methods to your current testbench.Signing up for an account is easy. With an Aldec account you'll have easy, one-click access to event registration, support, product downloads, evaluation licenses, recorded webinars, white papers, application notes and other resources. Simply provide your corporate e-mail address below - all account requests are verified and confirmed within 48 hours. If you already have an Aldec account, please Sign In below to download the file. Register Sign In
