Play WebinarTitle: VHDL Testbench Techniques that Leapfrog SystemVerilog with Guest Presenter, SynthWorksDescription: Verification can consume a good portion of a design cycle. What is needed is a methodology that facilitates thorough testing and timely completion. Attempting to achieve this, other verification methodologies (such as SystemVerilog's UVM) have gone in a direction that requires OO techniques and a specialist in verification. This webinar provides an overview of a VHDL methodology that is simple, powerful, and readable by both design and verification engineers. In addition, it supports all important testbench features: TLM (transaction level modeling), constrained random, functional coverage, intelligent testbenches, OSVVM, reuse, interfaces, scoreboards, concurrency and synchronization, and memory models.Signing up for an account is easy. With an Aldec account you'll have easy, one-click access to event registration, support, product downloads, evaluation licenses, recorded webinars, white papers, application notes and other resources. Simply provide your corporate e-mail address below - all account requests are verified and confirmed within 48 hours. If you already have an Aldec account, please Sign In below to download the file. Register Sign In
