Play WebinarTitle: Static Design Rule Checks in FPGA DesignDescription: Design Rule Checks have traditionally been associated with large ASIC designs, and have been used effectively to catch static violations as early as possible, thereby reducing debug time in the subsequent verification process. The benefits are the same when using DRC in the design methodology of FPGA. Aldec's ALINT, with its advanced check for the structural CDC issues, and extensive coverage of design rules based on recommended industry standards, addresses issues early in the design cycle.Signing up for an account is easy. With an Aldec account you'll have easy, one-click access to event registration, support, product downloads, evaluation licenses, recorded webinars, white papers, application notes and other resources. Simply provide your corporate e-mail address below - all account requests are verified and confirmed within 48 hours. If you already have an Aldec account, please Sign In below to download the file. Register Sign In
