Play WebinarTitle: Advanced RTL Debugging for Zynq SoC DesignsDescription: Presenter: Radek Nawrot, Aldec Software Product Manager Abstract: Designers of complex embedded applications based on Xilinx® Zynq™ device require a high-performance RTL simulation and debugging platform. In this webinar, you will learn several advanced RTL debugging methodologies and techniques that you can employ for your block-level and system level simulation. You will learn how to use Dataflow, Code Coverage, Xtrace and Waveform Contributors for analyzing the errors in your AXI-based Zynq designs. We welcome you to refer to the following Application Notes prior to the webinar: Xilinx AXI-Based IP Overview Simulating AXI BFM Examples Available in Xilinx CORE Generator Simulating AXI-based Designs in Riviera-PRO Performing Functional Simulation of Xilinx Zynq BFM in Riviera-PRO Agenda Embedded development flow between Xilinx Vivado™, SDK™, Riviera-PRO™ and TySOM™ Quick introduction to AXI Running Riviera-PRO from Vivado Code Coverage in simulation process Advance dataflow- design overview Bug injection – Xtrace in action Waveform with Contributors – seek bug in code Signing up for an account is easy. With an Aldec account you'll have easy, one-click access to event registration, support, product downloads, evaluation licenses, recorded webinars, white papers, application notes and other resources. Simply provide your corporate e-mail address below - all account requests are verified and confirmed within 48 hours. If you already have an Aldec account, please Sign In below to download the file. Register Sign In
