Play WebinarTitle: Verifying Resets and Reset Domain CrossingsDescription: Correct and clean reset strategy is essential for multi-million gate FPGA and ASIC devices. The possibility to start device operation from a potentially wrong state may cause malfunctions of hardware designs. Also, asynchronous resets may cause metastability effects, causing design malfunction and overheating due to increased power consumption. This webinar will describe Reset Structures and Reset Domain Crossings verification methodology and rules, demonstrated on demo designs using ALINT-PRO. The methodology behind ALINT-PRO includes careful static reset verification and ensuring valid design functionality (after resets de-assertion and an absence of metastability issues during reset assertion). Signing up for an account is easy. With an Aldec account you'll have easy, one-click access to event registration, support, product downloads, evaluation licenses, recorded webinars, white papers, application notes and other resources. Simply provide your corporate e-mail address below - all account requests are verified and confirmed within 48 hours. If you already have an Aldec account, please Sign In below to download the file. Register Sign In
