Play WebinarTitle: QEMU Co-emulation with FPGA Description: The FPGA or ASIC SoC require a robust pre-silicon hardware/software co-verification platform. Virtual platforms are used successfully as high-speed simulation vehicle but only for standard components like CPU, memory, timers and the like. The challenge emerges when custom IP-core is added to the design. Developing device drivers using HDL simulation is counterproductive and testing operating system and application stack is impossible. Hybrid co-emulation of standard machine virtualizer with FPGA bridges the gap in verification environment. QEMU is a generic and open source machine emulator that supports various computer hardware architectures including Intel x86 and ARM® Cortex® families. It can be connected with the Aldec HES-DVM™ emulation platform to provide a hybrid co-emulation environment for SoC designs. We will demonstrate the latest QEMU Bridge designed to provide connection between CPU subsystem in QEMU and custom hardware IP-Core run in the HES FPGA board and mapped as PCI Express device in QEMU. We will also show how software stack GDB debugger can be used in step-lock mode with the Aldec Hardware Debugger to provide full and deterministic view of the entire SoC. Signing up for an account is easy. With an Aldec account you'll have easy, one-click access to event registration, support, product downloads, evaluation licenses, recorded webinars, white papers, application notes and other resources. Simply provide your corporate e-mail address below - all account requests are verified and confirmed within 48 hours. If you already have an Aldec account, please Sign In below to download the file. Register Sign In
