Play WebinarTitle: Designing Finite State Machines for Safety Critical SystemsDescription: Finite State Machines (FSM) are a key part of safety-critical design control logic. During the operation of the FPGAs within the systems, single-event upsets or other radiation effects can cause the internal logic to flip to an incorrect value from ‘0’ to ‘1’ or ‘1’ to ‘0’ in a non-deterministic way, causing the system to fail. As transistors shrink, errors are becoming much more common; in a modern chip the devices are so small that cosmic rays or alpha particles can change the value of bits that are stored in FSM registers. In this webinar we will provide the various methods on how to develop robust and safe FSMs - from best practices in FSM design to highly reliable FSM design methods , allowing designers to develop state machines with transient errors detection and correction.Signing up for an account is easy. With an Aldec account you'll have easy, one-click access to event registration, support, product downloads, evaluation licenses, recorded webinars, white papers, application notes and other resources. Simply provide your corporate e-mail address below - all account requests are verified and confirmed within 48 hours. If you already have an Aldec account, please Sign In below to download the file. Register Sign In
