Play WebinarTitle: VHDL-2019: Just the New Stuff Part 3: RTL EnhancementsDescription: In this third webinar of the VHDL-2019: Just the New Stuff series we will focus on enhancements to VHDL's RTL coding capabilities. For a long time, VHDL was more verbose than other languages, however, much of that was fixed with VHDL2008. At the completion of VHDL-2008, VHDL was as concise as Verilog/SystemVerilog. VHDL-2019 continues working to make VHDL more concise and expressive. Two big RTL enhancements VHDL-2019 added are VHDL Interfaces and conditional compilation. This was covered in the Part 1, “VHDL-2019 Interfaces, Conditional Analysis, File IO, and The New Environment.” This presentation furthers the discussion of RTL enhancements and covers the following: Optional trailing semicolon at the end of interface list All interface lists are ordered Allow functions to know the output vector size Inferring signal and variable constraints from initial values Conditional expressions in object declarations Conditional return Component declaration syntax regularizationSigning up for an account is easy. With an Aldec account you'll have easy, one-click access to event registration, support, product downloads, evaluation licenses, recorded webinars, white papers, application notes and other resources. Simply provide your corporate e-mail address below - all account requests are verified and confirmed within 48 hours. If you already have an Aldec account, please Sign In below to download the file. Register Sign In
