Play WebinarTitle: CDC Verification with Hard IP BlocksDescription: Abstract Most FPGA designs contain configurable hard IP blocks supplied by FPGA vendors. These Hard IP blocks do not contain synthesizable RTL code, and therefore are excluded from advanced linting. In fact, this is a correct approach as hard IP blocks are assumed to be functionally stable and may be excluded from both static and dynamic verification. However, clock domain crossing verification still requires hard IP block constraining. These block-level constraints serve the following purposes: > Identify clock and reset ports, as well as required reset polarity and synchronization > Identify required clock phases for I/O ports > Describe hard IP as one of valid CDC synchronizer circuits During automated conversion of FPGA vendor projects, hard IPs were automatically constrained by the tool. These constraints are extracted from hard IP instance connectivity. In most cases, these IP-level constraints are not complete and require special attention from designers, as the top-level CDC analysis relies on the quality and completeness of hard IP constraints. In this webinar, we will present a robust hard IP design constraints development methodology. This methodology is illustrated for different IP block types and on the number of FPGA designs.Signing up for an account is easy. With an Aldec account you'll have easy, one-click access to event registration, support, product downloads, evaluation licenses, recorded webinars, white papers, application notes and other resources. Simply provide your corporate e-mail address below - all account requests are verified and confirmed within 48 hours. If you already have an Aldec account, please Sign In below to download the file. Register Sign In
