Play WebinarTitle: Turbocharge your FPGA Simulation Workflows Part 2: High-Performance RTL Simulation Workflow with Quartus and Active-HDLDescription: In part two of this three-part webinar series, we will show how to simulate an Altera design example. We will generate a design example from Quartus and simulate it using Active-HDL as the default simulator. We will discuss various tips that you can use to optimize compilation and simulation run times. The tips will be categorized from zero-cost effort to high-cost effort and, depending on your budget/resource constraints, you will have a path to speed up your simulation by a huge factor. We will turn on Profiler so that you can determine the bottlenecks in your design/testbench, and we will show how you to do a post-simulation debug using Waveform Viewer, Hierarchy, Object and Watch windows. Agenda: > Workflow with Quartus and Active-HDL > Tips on how to optimize simulation performance > Performance bottleneck analysis with Profiler > Post-simulation debugging with Waveform Viewer, Hierarchy and Watch window > Live demo > Q&ASigning up for an account is easy. With an Aldec account you'll have easy, one-click access to event registration, support, product downloads, evaluation licenses, recorded webinars, white papers, application notes and other resources. Simply provide your corporate e-mail address below - all account requests are verified and confirmed within 48 hours. If you already have an Aldec account, please Sign In below to download the file. Register Sign In
