Play Webinar

Title: Why Should Our Team be Using VHDL + OSVVM for Verification?

Description: This is a high-level presentation that identifies the key aspects of a modern verification methodology and shows how to achieve them with OSVVM. This is a great presentation to share with your management about why OSVVM (and OSVVM training) is important for your team. Developing and deploying a verification methodology can be costly and time consuming. Going without one will be even more costly due to bugs escaping into production hardware systems. Open Source VHDL Verification Methodology (OSVVM) provides the VHDL community with an already developed, open-source solution. OSVVM implements all of the capabilities of a modern verification methodology: transaction-based testing, a verification framework, verification components, self-checking tests, messaging handling, error tracking, requirements tracking, constrained random testing, scoreboards, functional coverage, co simulation with software, test automation, and a comprehensive set of test reports. This presentation examines how these capabilities will benefit your projects. SystemVerilog+UVM also provides a similar set of capabilities. Unfortunately, SV+UVM ended up absurdly complex to use – instead of using a module (entity/architecture in VHDL) with its built-in concurrency, SV+UVM uses OO, sequential code, and fork and join (to get concurrency). As a result, SV has failed to unify the design and verification communities. VHDL+OSVVM on the other hand uses entity/architectures to create verification components and libraries of subprograms (procedures and functions) to extend VHDL into a complete verification language. In doing this, OSVVM creates verification capabilities that rival SystemVerilog+UVM while at the same time it uses VHDL language elements that are familiar to VHDL design engineers. As a result, with VHDL+OSVVM and a good verification lead, any VHDL engineer can do verification as well as RTL design.

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