Active-HDL’s HDL Editor is a text editor for editing HDL source code. It contains features such as creating bookmarks, generating structure groups, autoformat/smart indentation, keyword coloring (VHDL, Verilog/SystemVerilog, C/C++, SystemC, OVA, and PSL), etc. Learn how to create a new HDL file with the New Design Wizard and how to utilize the HDE features within that created source file.

In this video we will look at console window, breakpoints, watch window, process window, call stack window, waveform and list viewer briefly among the vast debugging tools that exist on Active HDL.

FSM Coverage enables users to determine which states and transitions in the state machine diagram have been executed during simulation. To collect the FSM Coverage statistics, the HDL design code has to include SystemVerilog or Aldec proprietary pragmas indicating which constructs represent components of the state machine.

Active-HDL’s Accelerated Waveform Viewer is a high-performance tool dedicated to reading and producing simulation data in a graphical format that can be analyzed for the essential debugging process of hardware design. This video will demonstrate accessing the Waveform Viewer and the tool’s advanced features such as bookmarks, grouping signals, aliases, and altering signal properties.

Code Coverage is a debugging tool that analyzes code execution and can help us determine the completeness of the verification effort. Active-HDL allows verifying source code with multiple coverage tools including: Statement/Branch Coverage, Expression/Condition Coverage, FSM Coverage, and Path Coverage.

The Code2GraphicsTM converter is a tool designed for automatic translation of VHDL or Verilog/SystemVerilog source code into Active-HDL block and state diagrams. It analyzes VHDL, Verilog, or EDIF source files and generates one or more block diagram files depending on the number of design entities, modules, or cells found in the analyzed file.