Simulation and Debugging SystemVerilog Simulation SystemVerilog is a powerful IEEE approved language (IEEE 1800™) that enables significant improvements over its predecessor, Verilog HDL. This massive language combines many of the best features of VHDL, Verilog, and C++ and provides superior capabilities for system architecture, design, and verification. SystemVerilog breaks down into three major areas: hardware description, assertions, and the testbench language. Depending on the configuration of the tool and license configuration, designers can use features from these different areas of the language. (Click here to request a free SystemVerilog tutorial). SystemVerilog-based Universal Verification Methodology (UVM) is an industry-proven functional verification methodology approved by Accellera. Aldec provides a pre-compiled UVM library and SystemVerilog simulator to help customers meet the challenge of verifying today’s complex designs. VHDL 2019 Simulation VHDL IEEE 1076-2019 language standard is a powerful, more user-friendly upgrade from previous versions. VHDL-2019 adds important language enhancements for verification and design engineers and delivers many benefits from numerous added functionalities, including: Interfaces, Garbage collection, Conditional analysis, Shared variables on entities, Generics on protected types, Partially connected vectors in port maps, sequential block statements, Date and Time types. VHDL IEEE 1076-2019 is the biggest VHDL language standard change since the VHDL IEEE 1076-2008. Aldec includes support for VHDL-2019 in both Active-HDL™ and Riviera-PRO™ at no additional cost to customers with a valid maintenance contract and with a VHDL or mixed language simulation configuration. SystemC Co-Simulation SystemC is an environment that allows description and verification of digital systems using C++. Governed by IEEE 1666™-2005 and originally developed by the OSCI (Open SystemC Initiative), it is a library of classes and templates that provide hardware and system related features not available in standard C++. Both the Active-HDL and Riviera-PRO simulation and verification software solutions include support for C/C++ and SystemC and both offer designers seamless integration capability of HDL code and the various flavors of C. These IEEE-standardized interfaces allow simulation of HDL models with high-level C-based testbenches, instantiation of C models in HDL, connecting of custom visualization applications to HDL, performance of TLM and more. The C/C++/SystemC environment is ready to use upon installation. The installer includes a supported C/C++ compiler, header files and library files required by various types of C applications (SystemC, SystemC+SCV, PLI, VHPI). C applications can be compiled with a dedicated command that sets the required defines, paths to header files, libraries to be linked, etc. This allows engineers to focus on development, rather than on the caveats of C++ compilers. A powerful set of debugging tools is also available with Aldec’s solutions. Aldec simulators also contain a complete environment for developing and simulating SystemC Verification Library (SCV) applications. Recently popular SCV is built on the foundation of SystemC and Testbuilder and it supports advanced randomization techniques, transaction recording, etc. Header files and pre-compiled library files are delivered alongside with Aldec products. Testbench Generation The Testbench Generation tool is designed for automatic generation of testbench files based on the user-defined specification. It can generate the empty shell of the testbench (without stimulus) or it can generate the fully functional testbench with stimulus. Test vector file is needed to generate the testbench with stimulus. A testbench generates stimulus for the UUT entity on the basis of test vectors defined in this file. Also a testbench for any design unit can be generated from waveforms created in the waveform editor or during a simulation run. Benefits of using Testbench Generation: Powerful testbench generation tool speeds up functional verification Generated testbenches are completely editable for further modification Automatic generation of testbenches for state machines allows you to create a testbench that fully tests the state machine The SystemC Verification Library (SCV) delivered with ALDEC tools allows creating constrained and randomized stimulus. SCV combined with the transactor methodology offers the designer a powerful tool to create advanced testbench that automatically generated stimulus as well MATLAB/Simulink interface can be used to employ advanced testbenches with complex mathematical formulas used to stimulate unit under test(UUT)
