Static Linting

Aldec ALINT-PRO™ is an advanced Design Rule Checking (DRC) solution for RTL-level FPGA and ASIC designs that helps detect a wide variety of design issues, including poor coding styles, improper clock and reset management, improperly synchronized clock and reset domain crossings (CDC, RDC), simulation vs synthesis mismatches, incorrectly implemented finite state machines (FSM), poor testability, and other typical source code issues throughout the design flow. Aldec ALINT-PRO can be utilized both as a personal productivity tool at the design entry stage (by linting and debugging issues within independent units of RTL code in the background of the HDL editor) and as a part of the corporate verification flow running full linting on complete design hierarchy (formal code review, milestone signoff, regression testing flow, continuous integration environments). Another typical application of linting is to automate a review of external code, which could be coming from IP providers, subcontractors, and open-source communities. Aldec ALINT-PRO provides thorough quality checks of RTL code written in VHDL, Verilog, and SystemVerilog (design subset). The checks are performed against a set of design rules established by STARC® (The Semiconductor Technology Academic Research Center) from Japan, Reuse Methodology Manual (RMM), as well as rules developed by Aldec (ALDEC Basic, ALDEC Premium, ALDEC CDC, ALDEC SV, and DO-254). ALINT-PRO features a unique framework that combines all necessary tools for easy setup of design checks (the Policy), running linting, visualizing and waiving rule violations, and generating reports. The framework provides extended debugging capabilities for netlist and CDC/RDC issues analysis including: netlist visualization, clock and reset domains highlighting, clocks and resets trees visualization, navigation over detected clock and reset domain crossings and identified synchronization circuits, multi-dimensional cross-probing between structural, schematic, and violation views, and more. Similarly, ALINT-PRO offers intuitive exploration capabilities for the extracted finite state machines and the discovered related issues using graphical tools (FSM viewer, FSM graph).

design rule checking, netlist linting, rtl linting

Phase-Based Linting (PBL)

Phase-Based Linting (PBL) methodology, available in ALINT-PRO, inserts clear priorities into the design analysis process by reducing the total number of issues to be addressed and minimizing the number of design refinement iterations. This speeds up debugging time by 3—10X compared to the traditional approach. Phased-based design rule checking is optional, as it only attempts to organize the order of analysis and brings focus to a limited number of design aspects to be considered simultaneously.

PBL, design rule checking, netlist linting, rtl linting

Summary of key features:

Phase-Based Linting Methodology is implemented based on the Linting Flows
Linting Flow is a process – a set of phases that must be executed and completed sequentially
Every phase has its own set of rules and pass criteria (quality requirements)
Phases can be regular or optional and each of them typically addresses certain type of issues
Predefined flow templates are optimized and ready to use out-of-the-box
Flow templates often contain useful shortcuts for the most frequently executed tasks