White Papers

Comprehensive verification that can be provided by HDL simulators is good, but not ideal. What is necessary is a faster, safer, and more thorough verification environment that combines the robustness of an HDL simulator with the speed of FPGA prototyping boards. The goal is to put together the power of these two verification methodologies into one platform.

Simulation-to-Synthesis mismatch issues may cause malfunctions of physical devices. Even for functionally flawless RTL simulations, their physical implementation may contain critical design bugs. RTL Linting is the only way to locate and fix Simulation-to-Synthesis mismatch issues. The following article presents typical simulation-to-synthesis mismatch issues, illustrated by simple examples. For each one of described issues, the Lint checks are identified and explained.

The Federal Aviation Administration (FAA) recognizes the use of commonly used tools for FPGA design and verification such as RTL Simulator, Synthesis, Place & Route and Static Timing Analysis. For DAL A and B FPGAs, the FAA also recognizes other tools that improve design, verification, traceability and project management including Requirements Management, Traceability, Tests Management, Design Rule Checker, Clock Domain Crossings (CDC) Analysis, Code Coverage and FPGA Physical Test Systems.

Abstract: Aldec's Server Farm Manager (SFM) addresses ASIC regression testing issues for the fast, cost effective and high quality ASIC design verification.

With the latest FPGA technology advancements and release of large-scale FPGA devices, design teams are facing more challenges than ever in producing high quality HDL code. In order to save time during Functional Verification and Implementation stages, it becomes increasingly important to ensure the quality of design starting from the very early stages of the design process. In an ASIC design flow, a Lint tool (sometime referred to as Design Rule Checkers) ensures early-stage design quality, and maintaining this quality throughout the project lifecycle.

Abstract: Engineers working on modern, large FPGA designs face multiple challenges: changing languages, methodologies and tools implementing them. The fact that many designs now contain both hardware and software only adds to the confusion. This document tries to clarify the situation.

Clock domain crossing (CDC) issues cause significant amount of failures in ASIC and FPGA devices. As FPGA complexity and performance grows, the influence of CDC issues on design functionality grows even more. This paper outlines CDC issues and their solutions for FPGA designs. Various design techniques are presented together with real-life examples for Xilinx and Intel FPGA devices. More importantly, this paper summarizes the most important CDC guidelines for highly-reliable FPGA designs.

The increasing adoption of large, high-pin-count and high-speed FPGA devices means that right-first-time printed circuit board (PCB) design practices are more essential than ever for ensuring correct system operation. Typically, the PCB design takes place concurrently with the design and programming of the FPGA. Signal and pin assignments are initially made by the FPGA designer, and the board designer must correctly transfer these assignments to the symbols used in their system circuit schematics and board layout. As the board design progresses, pin reassignments may be needed to optimize the PCB layout. These reassignments must in turn be relayed back to the FPGA designer so that the new assignments can be processed through updated placement and routing of the FPGA design. To overcome these challenges, Zuken and Aldec provide an integrated design environment to support these design flows.

Growing customer requirements and technological abilities increase the design complexity of hardware and software. Time to market is shortening as well as the lifetime of new designs. In order to meet all those requirements a new approach to the design process is required.

DO-254 enforces a strict requirements-driven process for the development of commercial airborne electronic hardware. For DO-254, requirements must drive the design and verification activities, and requirements traceability helps to ensure this. This paper explains the rationale behind requirements traceability including its purpose and resulting benefits when done correctly.

The purpose of the document is to Guide the Qualification Process for Active-HDL Code Coverage tool.

Verification coverage by test is essential to satisfying the objectives of DO-254. However, verification of requirements by test during final board testing is challenging and time-consuming. This white paper explains the reasons behind these challenges, and provides recommendations how to overcome them. The recommendations center around Aldec’s unique device testing methodology that can significantly increase verification coverage by test.

Abstract: Debugging a design during emulation with a high level of visibility can be a challenge. This paper presents Aldec’s solution to this problem; a debugging environment for SCE-MI co-emulation that provides 100% signal visibility of the design running in an FPGA-based emulator. Debug probes captured intelligently from emulator retain original signals names and hierarchy paths to provide true RTL view of design in emulation.

Universal Verification Methodology (UVM) is one of the most popular approaches in using transactional testbench environment. The growth of SoC designs forces design and verification teams to use emulation as a way to speed-up verification process. Standard CoEmulation Modeling Interface (SCE-MI) provides ways to connect emulated design with transactional testbench. This paper describes how to use SCE-MI to create UVM test environment that is ready for both simulation and emulation.

Abstract: As the number of mobile and personal applications grows, usage of embedded processors becomes a necessity. New FPGA devices with so called soft or hard processor cores enable fast migration from the FPGA-only to the SoC applications and projects. This affects not only the hardware alone, but also the tools supporting the latest FPGA devices for SoC designers. Such tools are discussed within this document.

Abstract: PSL (Property Specification Language) is the easiest introduction to the world of design properties, assertions and coverage points to anybody familiar with VHDL (VHSIC Hardware Description Language). The designer of a digital circuit has the best understanding of the operation of the circuit, which makes her or him the best person to define properties that will fire assertion messages in case of incorrect design behavior during simulation or provide valuable feedback to the testbench creator by showing that all desired behaviors were covered during verification. For this reason, the use of embedded PSL properties and assertions is highly beneficial to the engineers and makes their designs better.

Abstract: PSL (Property Specification Language) is one of the easiest introductions to the world of design properties, assertions and coverage points to anybody familiar with Verilog HDL. The designer of a digital circuit has the best understanding of the operation of the circuit, which makes her or him the best person to define properties that will fire assertion messages in case of incorrect design behavior during simulation or provide valuable feedback to the testbench creator by showing that all desired behaviors were covered during verification. For this reason, the use of embedded PSL properties and assertions is highly beneficial to the engineers and makes their designs better.

Abstract: SVA (SystemVerilog Assertions) language is one of the easiest introductions to the world of design properties, assertions and coverage points to anybody familiar with Verilog HDL. The designer of a digital circuit has the best understanding of the operation of the circuit, which makes her or him the best person to define properties that will fire assertion messages in case of incorrect design behavior during simulation or provide valuable feedback to the testbench creator by showing that all desired behaviors were covered during verification. For this reason, the use of SVA properties and assertions directly in the design code is highly beneficial to the engineers and makes their designs better.

Clock domain crossings (CDCs) in FPGAs represent a probabilistic opportunity for failure. Functional simulation and static timing analysis tools are insufficient. Finding and addressing metastability and data incoherence around CDCs require static and dynamic analysis of FPGA designs. Aldec ALINT-PRO-CDC provides enhanced confidence that CDCs are located and fully mitigated.