FPGA Design Creation and FPGA Simulation
Active-HDL™ is a Windows® based, integrated FPGA design creation and simulation solution for team-based environments. Active-HDL’s integrated design environment (IDE) includes a full HDL and graphical design tool suite and RTL/gate-level mixed-language simulator for rapid deployment and verification of FPGA designs.
The design flow manager evokes 200+ EDA and FPGA tools, during design entry, simulation, synthesis and implementation flows and allows teams to remain within one common platform during the entire FPGA development process. Active-HDL supports industry leading FPGA devices from AMD, Intel, Lattice, Microchip, Quicklogic and more.
Top Features and Benefits
-
Unified Team-based Design Management maintains uniformity across local or remote teams
-
Configurable FPGA/EDA Flow Manager interfaces with 200+ vendors tools allows teams to remain on one platform throughout FPGA development
-
Quickly deploy designs by using Text, Schematic and State Machine
-
Distribute or deliver IPs using more secure and reliable Interoperable Encryption standard
-
Powerful common kernel mixed language simulator that supports VHDL, Verilog, SystemVerilog and SystemC
-
Ensure code quality and reliability using graphically interactive debugging and code quality tools
-
Perform metrics driven verification to identify unexercised parts of your design using Code Coverage analysis tools
-
Improve verification quality and find more bugs using ABV - Assertion-Based Verification (SVA, PSL)
- Ability to simulate advanced verification constructs like SV Functional Coverage, Constrained Randomization and UVM
-
Connect the gap between HDL simulation and high level mathematical modeling environment for DSP blocks using MATLAB®/Simulink® interface
-
Abstract design intelligence and represent them in easy to understand graphical form using HDL to schematic converter
-
Share designs quickly with auto-generate Design Documentation in HTML and PDF
- Featured
- Demonstration Video
3.2 3rd Party Flows: Vivado TCL store Integration
3.1 3rd Party Flows: Compiling Vivado Simulation Libraries- Recorded Webinar
- Taming Testbench Messaging and Error Reporting with OSVVM's Logs and Alerts
- Universal VHDL Verification Methodology (UVVM) – The standardized open source VHDL testbench architecture
- VHDL testbenches using models, scoreboards and transactions
- Creating an AXI4 Lite, Transaction Based VHDL Testbench with OSVVM
- UVVM steps up a gear: A review of some of the new features in this standardized VHDL verification methodology
- Creating Better Self-Checking FPGA Verification Tests with Open Source VHDL Verification Methodology (OSVVM)
- OSVVM: ASIC level VHDL Verification, Simple enough for FPGAs
- VHDL-2019: Just the New Stuff Part 3: RTL Enhancements
- VHDL-2019: Just the New Stuff Part 4: Testbench Enhancements
- Assertions-Based Verification for VHDL Designs
- Accelerating Verification Component development with OSVVM Model Independent Transactions
- The impact of AMC-152A guidance on design and verification process of DO-254 projects
- VHDL-2019: Just the New Stuff Part 1: Interfaces, Conditional Analysis, File IO, and The New Environment
- VHDL-2019: Just the New StuffPart 2: Protected Types and Verification Data Structures
- Application Note
- User-defined Design Management
- White Paper
- Corporate Standardization of FPGA Design Flow
- Aldec DO-254 Solutions Blueprint