Events Schedule

Webinars

 LocationDate 
Europe Webinar Aldec® and Zuken®: Pin Synchronization for Smooth Integration of PCB and FPGA Development Environments On-Line October 16 Register
Aldec® and Zuken®: Pin Synchronization for Smooth Integration of PCB and FPGA Development Environments On-Line October 16 Register
Euro AVMS I-04 Start Using Assertions in your Next Design On-Line October 23 Register
Start Using Assertions in your Next Design On-Line October 23 Register
Euro AVMS I-05 Aldec HDL Simulation Advantages over the Most Widely Marketed Simulators On-Line October 30 Register
Aldec HDL Simulation Advantages over the Most Widely Marketed Simulators On-Line October 30 Register

Seminars

 LocationDate 
SystemVerilog Assertions Language and Methodology Overview Seminar Sunnyvale, CA October 28 Register
SystemVerilog Assertions Language and Methodology Overview Seminar Sunnyvale, CA November 19 Register
SystemVerilog Assertions Language and Methodology Overview Seminar Sunnyvale, CA December 16 Register

Training

 LocationDate 
One Day Active-HDL Training Munchen, Germany November 10 Register

Trade Shows

 LocationDate 
SOPC World Bangalore, Dehli, Shenzhen, Hangzhou & Beijing October 14 - October 24 Register
Actel Space Forum 2008 Los Angeles, CA December 03 - December 03 Register
FPGA Summit San Jose, CA December 10 - December 11 Register