Active-HDL Configurations

With Active-HDL, you can mix different types of descriptions. Your design can include textual HDL code as well as block diagrams and state diagrams. More   

The Language Assistant is a tool designed to help you develop HDL, Handel-C, or SystemC source code, and Aldec macro commands. More   

Aldec simulators support several scripting methods varying in the level of abstraction and possible applications. More   

Perform common and repetitive task by simply moving the mouse. For example, you can zoom in and out by simply holding a right mouse button and moving your mouse up or down. More   

The Code2Graphics converter is a tool designed for automatic translation of text sources into Active-HDL block and state diagrams. More   

Active-HDL provides utilities for importing legacy schematic based designs from Xilinx Foundation Series, ViewLogic ViewDraw series, or any schematic tools that can output an EDIF netlist. More   

The ability to quickly document designed components is becoming critical with the increased complexity of designs, ubiquitous IP re-use, and design teams scattered across many floors, departments, or countries. More   

The Design Flow Manager configures, constrains and executes simulation, synthesis and implementation tools for all devices from Altera®, Atmel®, Lattice®, Microsemi™ (Actel), Quicklogic®, Xilinx® and more in one integrated development environment. More   

Active-HDL provides a powerful feature that allows communication and collaboration with a number of leading Source Revision Control systems. More   

Complex FPGA projects are often managed between various teams and require collaboration between team members. Its crucial to have a powerful design management tool that allows teams to collaborate on projects rapidly. More   

To prevent accidental design file deletions and to provide you with additional exchange and backup options, Active-HDL comes with an Archive Design feature that allows archiving the current design or entire workspace into a single ZIP file. More   

Designers can open multiple Active-HDL designs simultaneously and integrate them into one super-project. More   

Aldec and its Partners have worked together to create an integrated solution that offers PCB designers a smooth migration between PCB design capture and HDL based FPGA design management and simulation products. More   

The IP CORE Generator is a tool built-into Active-HDL that comes with a rich set of parameterized modules. They are ready-to-use in any VHDL- or Verilog-based system. More   

The Verilog PLI interface provides a standard mechanism to access and modify data in a simulated Verilog model. The PLI interface creates user-defined tasks and functions that interact with Active-HDL. More   

Powerful testbench generation automation features have been provided to speed functional verification. A testbench for any design unit can be generated from waveforms created in the waveform editor or during a simulation run. More   

An auxiliary verification tool built-in to Active-HDL that creates testbenches used to test the HDL code generated by the State Diagram Editor. More   

ALDEC simulators provide comprehensive support of the IEEE 1076-1993 Standard, IEEE 1076™-2002 VHDL standard and majority of just published IEEE 1076™-2008 Standard. More   

ALDEC simulators provide full support of the IEEE 1364-2005 Standard. To enable simulation of a large variety of Verilog designs, both legacy and new, ALDEC simulators can be set to work in Verilog ’95, 2001 and 2005 modes. More   

SystemVerilog is a set of extensions to the Verilog HDL that allow higher level of modeling and efficient verification of large digital systems. More   

Simulation of netlist in EDIF 2 0 0 format is supported by most Aldec Simulators. More   

Verification Libraries (OSVVM, UVVM, cocotb) More   

SystemC is a C library that extends C to enable hardware modeling. Although strictly a C class library, SystemC is sometimes viewed as being a language in its own right More   

SystemVerilog IEEE 1800™-2012 (Verification) for Active-HDL More   

Active-HDL includes simulation optimization features for both VHDL and Verilog which accelerate the simulation and cut simulation time significantly. More   

Most ALDEC simulator configurations support mixed (VHDL and Verilog) designs, but single language (VHDL-only or Verilog-only) configurations are also available. More   

The Verilog PLI (Programming Language Interface) and VPI (Verilog Procedural Interface) provide a standard mechanism to access and modify data in a simulated Verilog model. More   

The VHPI interface provides a standard means to access data in VHDL models elaborated in Active-HDL and Riviera-PRO. More   

Language Interface Wizard (PLI/VPI/VHPI/DPI) More   

The DPI-C wizard allows you to enter the names of DPI-C tasks and functions, their arguments (name, type, mode, and, optionally, the default value and range). More   

Library protection offers four security levels when compiled models are distributed in the form of library files without releasing their source code. More   

Using standard design source encryption is a much easier form of managing IP creation and delivery than any kind of binary file encryption. Riviera-PRO supports standard methodology introduced in IEEE Std. 1364-2005. More   

Using standard design source encryption is a much easier form of managing IP creation and delivery than any kind of binary file encryption. Riviera-PRO supports standard methodology introduced in IEEE Std. 1076-2008. More   

IEEE 1735™ Interoperable Encryption More   

The VCD (Value Change Dump) file format is specified in the IEEE Std. 1364-1995 standard. The VCD file is an ASCII file containing header information, variable definitions, and variable value changes. More   

VSimSA is a standalone VHDL/Verilog simulation environment designed for batch processing. More   

The Profiler identifies design units or code sections that put the greatest strain on the simulator. This information is valuable for optimizing the simulation environment and improving performance. More   

Pre-compiled libraries for various FPGA vendors (Microsemi™ (Actel), Altera®, Lattice®, Xilinx® and others) are provided with Active-HDL. More   

Aldec simulators support the SecureIP methodology of IP delivery implemented in Xilinx tools. More   

Server Farm Manager is an advanced tool working on the local network that allows users to schedule tasks and then execute them automatically on the selected computers available on the network. More   

The ability for the simulator to run at 64-bit bus throughput application speeds and utilize extended memory. More   

Traceability from Requirements to HDL Source Code More   

The Design Hierarchy Viewer is a tool that allows designers to display the project's structure without its elaboration. More   

Stepping through source code is one of the most common debugging procedures. Stepping is executing code one line at a time More   

Simulations can be stopped on a breakpoint. Aldec supports both breakpoints in the source code as well as signal breakpoints. More   

Aldec simulators can maintain communication with graphical design sources during simulation and can push live values of ports and signals to the Block Diagram Editor, where they can be displayed in the shape of colorful probes. More   

The Memory Viewer is a debugging tool that has been designed to display memory objects defined in an active design. More   

Active-HDL provides features that help users to debug their bubble diagrams, including object sorter, diagram report, trace over transition, current state highlight, etc. More   

The Accelerated Waveform Viewer is a high performance tool for graphical presentation of simulation data stored in a binary simulation database (*.asdb). More   

In large designs where multiple signals must be observed during simulation, keeping them in one waveform window is inconvenient: since all signals cannot fit in one window, frequent scrolling is required to get to the desired waveform data. More   

When quick checking of some parts of a large design is required, creating a testbench is not economical: testbenches work best while testing complete designs during multiple runs of simulation. More   

A fast Waveform Viewer is an indispensable analysis tool, but signal data must be modified from time to time. More   

Post Simulation Debug is an advanced feature that allows users to observe the simulation results after the simulation has been finished. More   

The C Code Debug option is a feature that allows designers to debug PLI, VHPI, SystemC, or C/C++ source code with the open-source gdb debugger. More   

The Signal Agent in VHDL allows monitoring and driving VHDL signals from any VHDL block. Signals do not have to be routed via the interface or declared in global packages. More   

X-Trace helps you quickly identify the cause of unexpected values by reporting information on changes from valid to unknown, uninitialized, or user-defined values in the simulated model. More   

The Dataflow window is a powerful tool that allows designers to explore the connectivity of an active design and analyze dataflow among instances, concurrent statements, signals, nets, and registers during simulation. More   

The stand-alone Waveform Viewer can be used to: display simulation results created in previous simulation runs and display simulation results on the fly, while simulation is still in progress. More   

Integration with Riviera-PRO and ALINT is one-click interface that allows users to invoke Riviera-PRO and ALINT from within Active-HDL. Using this integration, users can export their Active-HDL projects to Riviera-PRO and ALINT during different design stages, such as simulation and linting. More   

Design and verification engineers who implemented assertions and covers in their project can observe their behavior during regular simulation and debugging in multiple windows. More   

Code Coverage is a debugging tool that aids the verification process. More   

Specification of properties and their use in assertions and functional coverage is the essential element of designing modern systems and their verification algorithms. More   

Functional Coverage can provide information about the quality of the design verification process. More   

Aldec® ALINT-PRO™ is a design verification solution for RTL code written in VHDL, Verilog, and SystemVerilog. The solution performs static analysis based on RTL and SDC™ source files uncovering critical design issues early in the design cycle. More   

Dual-language rule library driven by customer requests. More   

Rules for SystemVerilog RTL design subset that cover new varieties of harmful RTL defects related to new language constructs. More   

Language-independent rules for CDC and RDC verification aimed to avoid metastability issues in complex designs. More   

The most comprehensive rule library covering large variety of topics. More   

Set of rules that should be used to improve design compliance with DO-254. More   

Dual-language rule library automates the methodology for effective design reuse and verification. More   

The Simulink Interface simplifies verification of hardware designs by providing robust visualization and analysis toolsets. More   

Aldec simulators integrate The MathWorks' intuitive MATLAB language and a technical computing environment. More   

Node Locked License More   

One Year Time Based License (TBL) grants a designer a license to use the product for a period of one year. A 1 year support contract is included with the purchase of TBL license. More   

A perpetual license is a license with no expiration date. A 1 year support contract is included with the purchase of perpetual license. More   

Builds are tested on all the latest platforms to ensure correct operation on users' workstations. More