Aldec @ DAC 2020: Presenting RISC-V Verification Methodologies and Solutions

By integrating Aldec’s Riviera-PRO™ with Codasip’s Studio™, verification of RISC-V CPU custom instructions at the RTL implementation level becomes an incredibly powerful platform for RISC-V processor deployment. In this presentation, we will show in Studio, how users can describe the RISC-V architecture and add custom instructions using CodAL high level language, modify the pipeline, configure random instruction generator, auto-generate the HDK, SDK, RTL implementation and C++ reference model and UVM environment, start RTL simulation, setup breakpoints and debug. We will then show in Riviera-PRO, how users can run RTL simulation and debug applications and core architecture, inspect simulation waveforms, use the UVM Graph & Toolbox to view the graphical representation of the UVM components, objects and the transaction level modeling (TLM) connections between them, giving the user an overall perspective of the testbench architecture and the dataflow. We will also show how you can collect and analyze both functional coverage and code coverage.

This presentation showcases the simulation of the Ibex core, which is a 2-stage in-order 32b RISC-V processor core. It has been designed to be small and efficient. The simulation of the SV/UVM testbench for verification of the Ibex core uses Riviera-PRO. This SV/UVM testbench uses the open source RISCV-DV random instruction generator, which generates compiled instruction binaries. We then load these binaries into a simple memory model which then stimulates the Ibex core in Riviera-PRO to run this program in that memory. We then compares the ibex core simulation trace log against a golden model generated by an Instruction Set Simulator (ISS) trace log to check for correctness of execution. The testbench is created based on its usage of the RISCV-DV random instruction generator developed by Google. There are two memory interface agents that are instantiated within the testbench, one for the instruction fetch interface, and the second for the Load-Store Unit (LSU) interface. These agents which run the slave sequences wait for memory requests from the core, and then grant the requests for instructions and data. There is also an Interrupt Interface Agent which is used to drive stimulus onto the Ibex core’s interrupt pins randomly during test execution. The testbench instantiates a single instance of the memory model that it loads the compiled assembly test program into at the beginning of each test. This serves as a unified instruction/data memory that processes all requests from both of the memory interface agents. The tests located in the Tests and Sequence Library are the main sources of external stimulus generation and checking for this testbench, as the memory interface slave sequences simply serve the core’s memory requests.The tests are all extended from core_ibex_base_test, and manage the entire flow for a single test, from loading the compiled assembly binary program into the testbench memory model, to checking the Ibex core status while the test is running and handling test timeouts. The sequences here are used to drive interrupt and debug stimulus into the core.The goal of this testbench is to fully verify the Ibex core with 100% coverage. Riviera-PRO can be used to examine the coverage results, visualize the UVM environment and aide in the debug of the verification environment.

The entire processor industry is currently going through a paradigm shift - new generations of domain-specific proprietary processor cores based on the open-source RISC-V ISA are now being developed by various industry-leading semiconductor companies. Additionally, open-source RISC-V processor cores such as SweRV, Ibex and Pulp are now available, and they are actively being developed in various open-source Github communities. Static verification or linting is a standard part of the tool flow for any processor-based designs to help engineers develop highly robust code in both IP and SoC levels. Static linting based on industry-best practice coding standards are critical in ensuring best-practice coding styles, efficient synthesis and timing closure, avoid simulation-to-synthesis mismatches, and proper usage of SystemVerilog constructs and data types. In this presentation, we will demonstrate how to statically verify RISC-V IP designs with the new ALINT-PRO RISC-V ruleset.

The RISC-V ISA has opened tremendous opportunities creating a breeze of fresh air in the ARM dominated design houses of embedded SoC projects. We didn’t have to wait long until the first RTL implementations of the RISC-V processor were started (both open source and commercial). Currently there are several open source projects of RISC-V CPU cores. There is however a verification gap between the open source fabless design and the ones that are intended to be taped out. The HDL/RTL simulation that works well for research and open source projects is not sufficient in case of huge investments in chip fabrication where designs must be verified exhaustively. In this session we will present how FPGA hardware-assisted verification such as simulation acceleration, emulation and prototyping can be used at different verification stages to bridge the verification gap, increase functional test coverage and enable true hardware-software co-verification of RISC-V cores and SoCs.

Together with Aldec, PLDA and Avery Design Systems, we will present and demo our newest PCIe 5.0 IP + VIP UVM simulation and debugging environment. PLDA’s PCIE 5.0 XpressRich includes internal datapath automatic scaling, configurable pipelining, Rx stream mode for custom credit management, L1 PM substates, dynamically adjustable application clock frequency and clock/power gating. Avery’s APCIe-Xactor includes best-in-class Verification IP for PCIe GEN5, native SystemVerilog and UVM support, native randomization, layer wise protocol and debug tracker and 35+ callbacks for error injection. In Aldec’s Riviera-PRO you can run RTL simulation and debug, visualize simulation waveforms, view the graphical representation of the UVM components, objects and the transaction level modeling (TLM) connections, and as well as use code coverage to analyze the efficiency of the UVM tests for exercising various parts of the RTL code.

Hardware assisted verification became much more affordable due to the availability of high capacity FPGAs (like Xilinx Virtex UltraScale US440) and their adoption for emulation verification environments in Aldec’s HES-DVM. One of the advantages of FPGA-based emulation is that it’s much more flexible than traditional processor-based when it comes to connecting external peripherals. In this presentation we will demonstrate how to take advantage of the FPGA platform to build the PCI Express speed adapter and connect the emulated System-on-Chip design with the external PCIe-based Network Interface Card that runs at its target speed and provides connection of the SoC to the real LAN network traffic.