Resources

Hardware Designers are usually very busy doing their work and have little time left for experimentation with new methodologies. Unfortunately for them, official documentation of UVM (Universal Verification Methodology) was written by Verification Engineers for Verification Engineers, concentrating on high-level features and completely neglecting lower-level details such as connecting UVM testbench to your design. Our webinar starts with solid review of SystemVerilog interfaces with special attention paid to Virtual Interfaces. Then it proceeds to Sequences and other Data Items, processed by Sequencers and fed to the design under test via Drivers. The role of Monitors and Scoreboards in analysis of results is explained. The presentation concludes with environment configuration and running test from the top-level module. Play webinar   

Cocotb is a CO-routine based CO-simulation Testbench environment for verifying VHDL/Verilog RTL using Python. It is an open-source environment and hosted on Github. . It uses the same design-reuse and functional verification concepts like UVM, however is implemented in Python. In this webinar, we will introduce Cocotb, and will outline how Cocotb can provide significant savings in development time, promote code re-use and ultimately reduce project time-to-market and total development cost.  Play webinar